文件名称:mem-ctrl-rtl
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- 上传时间:2012-11-16
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文件大小:43.23kb
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实现对ddr的控制,可以在fpga的仿真环境下跑程序,并有testbench可以参考-implement ddr control
相关搜索: VHDL DDR
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下载文件列表
rtl/CVS/Entries
rtl/CVS/Entries.Extra
rtl/CVS/Entries.Extra.Old
rtl/CVS/Entries.Old
rtl/CVS/Repository
rtl/CVS/Root
rtl/CVS/Template
rtl/mmc_tb.v
rtl/mmc_tb.v.bak
rtl/verilog/CVS/Entries
rtl/verilog/CVS/Entries.Extra
rtl/verilog/CVS/Entries.Extra.Old
rtl/verilog/CVS/Entries.Old
rtl/verilog/CVS/Repository
rtl/verilog/CVS/Root
rtl/verilog/CVS/Template
rtl/verilog/mc_adr_sel.v
rtl/verilog/mc_cs_rf.v
rtl/verilog/mc_defines.v
rtl/verilog/mc_dp.v
rtl/verilog/mc_incn_r.v
rtl/verilog/mc_mem_if.v
rtl/verilog/mc_obct.v
rtl/verilog/mc_obct_top.v
rtl/verilog/mc_rd_fifo.v
rtl/verilog/mc_refresh.v
rtl/verilog/mc_rf.v
rtl/verilog/mc_timing.v
rtl/verilog/mc_top.v
rtl/verilog/mc_wb_if.v
rtl/verilog/CVS
rtl/CVS
rtl/verilog
rtl
rtl/CVS/Entries.Extra
rtl/CVS/Entries.Extra.Old
rtl/CVS/Entries.Old
rtl/CVS/Repository
rtl/CVS/Root
rtl/CVS/Template
rtl/mmc_tb.v
rtl/mmc_tb.v.bak
rtl/verilog/CVS/Entries
rtl/verilog/CVS/Entries.Extra
rtl/verilog/CVS/Entries.Extra.Old
rtl/verilog/CVS/Entries.Old
rtl/verilog/CVS/Repository
rtl/verilog/CVS/Root
rtl/verilog/CVS/Template
rtl/verilog/mc_adr_sel.v
rtl/verilog/mc_cs_rf.v
rtl/verilog/mc_defines.v
rtl/verilog/mc_dp.v
rtl/verilog/mc_incn_r.v
rtl/verilog/mc_mem_if.v
rtl/verilog/mc_obct.v
rtl/verilog/mc_obct_top.v
rtl/verilog/mc_rd_fifo.v
rtl/verilog/mc_refresh.v
rtl/verilog/mc_rf.v
rtl/verilog/mc_timing.v
rtl/verilog/mc_top.v
rtl/verilog/mc_wb_if.v
rtl/verilog/CVS
rtl/CVS
rtl/verilog
rtl
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