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文件名称:vga_lcd_latest.tar

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.71mb
  • 已下载：
    0次
  • 提 供 者：
    li***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

此VGA/LCD控制器是revB.3版本的基于WISHBONE总线，适用于驱动CRT和LCD显示屏的嵌入式VGA驱动。-VGA/LCD Controller core is a WISHBONE revB.3 compliant embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limited only by the available WISHBONE bandwidth.
相关搜索： WISHBONE

(系统自动生成,下载前可以参看下载内容)

下载文件列表

./
./vga_lcd/
./vga_lcd/tags/
./vga_lcd/tags/rel_1/
./vga_lcd/tags/rel_1/software/
./vga_lcd/tags/rel_1/software/include/
./vga_lcd/tags/rel_1/software/include/oc_vga_lcd.h
./vga_lcd/tags/rel_1/bench/
./vga_lcd/tags/rel_1/bench/verilog/
./vga_lcd/tags/rel_1/bench/verilog/wb_mast_model.v
./vga_lcd/tags/rel_1/bench/verilog/wb_model_defines.v
./vga_lcd/tags/rel_1/bench/verilog/wb_slv_model.v
./vga_lcd/tags/rel_1/bench/verilog/test_bench_top.v
./vga_lcd/tags/rel_1/bench/verilog/tests.v
./vga_lcd/tags/rel_1/bench/verilog/sync_check.v
./vga_lcd/tags/rel_1/doc/
./vga_lcd/tags/rel_1/doc/src/
./vga_lcd/tags/rel_1/doc/src/vga_core_enh.doc
./vga_lcd/tags/rel_1/doc/vga_core.pdf
./vga_lcd/tags/rel_1/rtl/
./vga_lcd/tags/rel_1/rtl/verilog/
./vga_lcd/tags/rel_1/rtl/verilog/vga_wb_slave.v
./vga_lcd/tags/rel_1/rtl/verilog/vga_wb_master.v
./vga_lcd/tags/rel_1/rtl/verilog/vga_colproc.v
./vga_lcd/tags/rel_1/rtl/verilog/vga_defines.v
./vga_lcd/tags/rel_1/rtl/verilog/vga_pgen.v
./vga_lcd/tags/rel_1/rtl/verilog/vga_curproc.v
./vga_lcd/tags/rel_1/rtl/verilog/generic_spram.v
./vga_lcd/tags/rel_1/rtl/verilog/vga_cur_cregs.v
./vga_lcd/tags/rel_1/rtl/verilog/vga_fifo.v
./vga_lcd/tags/rel_1/rtl/verilog/ro_cnt.v
./vga_lcd/tags/rel_1/rtl/verilog/timescale.v
./vga_lcd/tags/rel_1/rtl/verilog/vga_csm_pb.v
./vga_lcd/tags/rel_1/rtl/verilog/vga_enh_top.v
./vga_lcd/tags/rel_1/rtl/verilog/vga_fifo_dc.v
./vga_lcd/tags/rel_1/rtl/verilog/vga_tgen.v
./vga_lcd/tags/rel_1/rtl/verilog/ud_cnt.v
./vga_lcd/tags/rel_1/rtl/verilog/generic_dpram.v
./vga_lcd/tags/rel_1/rtl/verilog/vga_vtim.v
./vga_lcd/tags/rel_1/rtl/vhdl/
./vga_lcd/tags/rel_1/rtl/vhdl/colproc.vhd
./vga_lcd/tags/rel_1/rtl/vhdl/fifo.vhd
./vga_lcd/tags/rel_1/rtl/vhdl/vga.vhd
./vga_lcd/tags/rel_1/rtl/vhdl/vga_and_clut_tstbench.vhd
./vga_lcd/tags/rel_1/rtl/vhdl/pgen.vhd
./vga_lcd/tags/rel_1/rtl/vhdl/csm_pb.vhd
./vga_lcd/tags/rel_1/rtl/vhdl/counter.vhd
./vga_lcd/tags/rel_1/rtl/vhdl/fifo_dc.vhd
./vga_lcd/tags/rel_1/rtl/vhdl/wb_slave.vhd
./vga_lcd/tags/rel_1/rtl/vhdl/vtim.vhd
./vga_lcd/tags/rel_1/rtl/vhdl/vga_and_clut.vhd
./vga_lcd/tags/rel_1/rtl/vhdl/dpm.vhd
./vga_lcd/tags/rel_1/rtl/vhdl/tgen.vhd
./vga_lcd/tags/rel_1/rtl/vhdl/wb_master.vhd
./vga_lcd/tags/rel_1/sim/
./vga_lcd/tags/rel_1/sim/rtl_sim/
./vga_lcd/tags/rel_1/sim/rtl_sim/bin/
./vga_lcd/tags/rel_1/sim/rtl_sim/bin/Makefile
./vga_lcd/tags/rel_1/syn/
./vga_lcd/tags/rel_1/syn/bin/
./vga_lcd/tags/rel_1/syn/bin/read.dc
./vga_lcd/tags/rel_1/syn/bin/lib_spec.dc
./vga_lcd/tags/rel_1/syn/bin/design_spec.dc
./vga_lcd/tags/rel_1/syn/bin/comp.dc
./vga_lcd/tags/beta/
./vga_lcd/tags/beta/colproc.vhd
./vga_lcd/tags/beta/vga_24bpp_sim.do
./vga_lcd/tags/beta/fifo.vhd
./vga_lcd/tags/beta/vga.vhd
./vga_lcd/tags/beta/vga_8bpp_pc_sim.do
./vga_lcd/tags/beta/vga_16bpp_sim.do
./vga_lcd/tags/beta/pgen.vhd
./vga_lcd/tags/beta/vga_wave.do
./vga_lcd/tags/beta/counter.vhd
./vga_lcd/tags/beta/vga_8bpp_gray_sim.do
./vga_lcd/tags/beta/fifo_dc.vhd
./vga_lcd/tags/beta/wb_slave.vhd
./vga_lcd/tags/beta/vtim.vhd
./vga_lcd/tags/beta/dpm.vhd
./vga_lcd/tags/beta/tgen.vhd
./vga_lcd/tags/beta/wb_master.vhd
./vga_lcd/tags/rel_19/
./vga_lcd/tags/rel_19/software/
./vga_lcd/tags/rel_19/software/include/
./vga_lcd/tags/rel_19/software/include/oc_vga_lcd.h
./vga_lcd/tags/rel_19/bench/
./vga_lcd/tags/rel_19/bench/verilog/
./vga_lcd/tags/rel_19/bench/verilog/wb_mast_model.v
./vga_lcd/tags/rel_19/bench/verilog/wb_model_defines.v
./vga_lcd/tags/rel_19/bench/verilog/wb_slv_model.v
./vga_lcd/tags/rel_19/bench/verilog/test_bench_top.v
./vga_lcd/tags/rel_19/bench/verilog/wb_b3_check.v
./vga_lcd/tags/rel_19/bench/verilog/tests.v
./vga_lcd/tags/rel_19/bench/verilog/sync_check.v
./vga_lcd/tags/rel_19/doc/
./vga_lcd/tags/rel_19/doc/src/
./vga_lcd/tags/rel_19/doc/src/vga_core_enh.doc
./vga_lcd/tags/rel_19/doc/vga_core.pdf
./vga_lcd/tags/rel_19/sim/
./vga_lcd/tags/rel_19/sim/rtl_sim/
./vga_lcd/tags/rel_19/sim/rtl_sim/bin/
./vga_lcd/tags/rel_19/sim/rtl_sim/bin/Makefile
./vga_lcd/tags/rel_19/syn/
./vga_lcd/tags/rel_19/syn/bin/
./vga_lcd/tags/rel_19/syn/bin/read.dc
./vga_lcd/tags/rel_19/syn/bin/lib_spec.dc
./vga_lcd/tags/rel_19/syn/bin/design_spec.dc
./vga_lcd/tags/rel_19/syn/bin/comp.dc
./vga_lcd/branches/
./vga_lcd/web_uploads/
./vga_lcd/web_uploads/index.shtml
./vga_lcd/web_uploads/vga_core.pdf
./vga_lcd/web_uploads/block_diagram.jpg
./vga_lcd/web_uploads/block_diagram.gif
./vga_lcd/trunk/
./vga_lcd/trunk/software/
./vga_lcd/trunk/software/include/
./vga_lcd/trunk/software/include/oc_vga_lcd.h
./vga_lcd/trunk/bench/
./vga_lcd/trunk/bench/verilog/
./vga_lcd/trunk/bench/verilog/wb_mast_model.v
./vga_lcd/trunk/bench/verilog/wb_model_defines.v
./vga_lcd/trunk/bench/verilog/wb_slv_model.v
./vga_lcd/trunk/bench/verilog/test_bench_top.v
./vga_lcd/trunk/bench/verilog/wb_b3_check.v
./vga_lcd/trunk/bench/verilog/tests.v
./vga_lcd/trunk/bench/verilog/sync_check.v
./vga_lcd/trunk/doc/
./vga_lcd/trunk/doc/src/
./vga_lcd/trunk/doc/src/vga_core_enh.doc
./vga_lcd/trunk/doc/vga_core.pdf
./vga_lcd/trunk/rtl/
./vga_lcd/trunk/rtl/verilog/
./vga_lcd/trunk/rtl/verilog/vga_wb_slave.v
./vga_lcd/trunk/rtl/verilog/vga_wb_master.v
./vga_lcd/trunk/

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