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文件名称:xapp265

  • 所属分类：
    Project Design
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    355kb
  • 已下载：
    1次
  • 提 供 者：
    jega*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

High-Speed Data Serialization and

Deserialization(840 Mb/s LVDS)

for xilinx fpga
相关搜索： lvds fpga LVDS FPGA LVDS serdes_4b_1to7 serdes_4b_7to1 xilinx fpga FPGA SERIALIZATION

(系统自动生成,下载前可以参看下载内容)

下载文件列表

7to1/
7to1/basic_design/
7to1/basic_design/verilog/
7to1/basic_design/verilog/constraints/
7to1/basic_design/verilog/design_files/
7to1/basic_design/verilog/simulation/
7to1/basic_design/vhdl/
7to1/basic_design/vhdl/constraints/
7to1/basic_design/vhdl/design_files/
7to1/basic_design/vhdl/simulation/
7to1/demo_board/
7to1/demo_board/verilog/
7to1/demo_board/verilog/constraints/
7to1/demo_board/verilog/design_files/
7to1/demo_board/verilog/simulation/
7to1/demo_board/vhdl/
7to1/demo_board/vhdl/constraints/
7to1/demo_board/vhdl/design_files/
7to1/demo_board/vhdl/simulation/
8to1/
8to1/basic_design_16bit/
8to1/basic_design_16bit/example_ucf/
8to1/basic_design_16bit/verilog/
8to1/basic_design_16bit/verilog/2v1000_ucf_synpl_leo/
8to1/basic_design_16bit/verilog/design_files/
8to1/basic_design_16bit/verilog/simulation/
8to1/basic_design_16bit/vhdl/
8to1/basic_design_16bit/vhdl/2v1000_ucf_fpgax_xst/
8to1/basic_design_16bit/vhdl/2v1000_ucf_synpl_leo/
8to1/basic_design_16bit/vhdl/design_files/
8to1/basic_design_16bit/vhdl/simulation/
8to1/basic_design_20bit/
8to1/basic_design_20bit/example_ucf/
8to1/basic_design_20bit/verilog/
8to1/basic_design_20bit/verilog/2v1000_ucf_synpl_leo/
8to1/basic_design_20bit/verilog/design_files/
8to1/basic_design_20bit/verilog/simulation/
8to1/basic_design_20bit/vhdl/
8to1/basic_design_20bit/vhdl/2v1000_ucf_fpgax_xst/
8to1/basic_design_20bit/vhdl/2v1000_ucf_synpl_leo/
8to1/basic_design_20bit/vhdl/design_files/
8to1/basic_design_20bit/vhdl/simulation/
8to1/basic_design_4bit/
8to1/basic_design_4bit/example_ucf/
8to1/basic_design_4bit/verilog/
8to1/basic_design_4bit/verilog/design_files/
8to1/basic_design_4bit/verilog/simulation/
8to1/basic_design_4bit/verilog/ucf_synpl_leo/
8to1/basic_design_4bit/vhdl/
8to1/basic_design_4bit/vhdl/design_files/
8to1/basic_design_4bit/vhdl/simulation/
8to1/basic_design_4bit/vhdl/ucf_fpgax_xst/
8to1/basic_design_4bit/vhdl/ucf_synpl_leo/
8to1/demo_board/
8to1/demo_board/verilog/
8to1/demo_board/verilog/design_files/
8to1/demo_board/verilog/simulation/
8to1/demo_board/verilog/ucf_fpgax_xst/
8to1/demo_board/verilog/ucf_synpl_leo/
8to1/demo_board/vhdl/
8to1/demo_board/vhdl/design_files/
8to1/demo_board/vhdl/simulation/
8to1/demo_board/vhdl/ucf_fpgax_xst/
8to1/demo_board/vhdl/ucf_synpl_leo/
xapp265/
xapp265/7to1/
xapp265/7to1/basic_design/
xapp265/7to1/basic_design/README.TXT
xapp265/7to1/basic_design/verilog/
xapp265/7to1/basic_design/verilog/constraints/
xapp265/7to1/basic_design/verilog/constraints/top4_2v1000_fg456.ucf
xapp265/7to1/basic_design/verilog/constraints/top8_2v1000_fg456.ucf
xapp265/7to1/basic_design/verilog/design_files/
xapp265/7to1/basic_design/verilog/design_files/m2_1p.v
xapp265/7to1/basic_design/verilog/design_files/mux2_1.v
xapp265/7to1/basic_design/verilog/design_files/serdes_4b_1to7.v
xapp265/7to1/basic_design/verilog/design_files/serdes_4b_1to7_wrapper.v
xapp265/7to1/basic_design/verilog/design_files/serdes_4b_1to7_wrapper_286.v
xapp265/7to1/basic_design/verilog/design_files/serdes_4b_7to1.v
xapp265/7to1/basic_design/verilog/design_files/serdes_4b_7to1_wrapper.v
xapp265/7to1/basic_design/verilog/design_files/serdes_4b_7to1_wrapper_285.v
xapp265/7to1/basic_design/verilog/design_files/serdes_8b_1to7_wrapper.v
xapp265/7to1/basic_design/verilog/design_files/serdes_8b_1to7_wrapper_484.v
xapp265/7to1/basic_design/verilog/design_files/serdes_8b_7to1_wrapper.v
xapp265/7to1/basic_design/verilog/design_files/serdes_8b_7to1_wrapper_483.v
xapp265/7to1/basic_design/verilog/design_files/top4.v
xapp265/7to1/basic_design/verilog/design_files/top8.v
xapp265/7to1/basic_design/verilog/simulation/
xapp265/7to1/basic_design/verilog/simulation/tbtop4u.v
xapp265/7to1/basic_design/verilog/simulation/tbtop8u.v
xapp265/7to1/basic_design/verilog/simulation/TOP4U.DO
xapp265/7to1/basic_design/verilog/simulation/TOP8U.DO
xapp265/7to1/basic_design/vhdl/
xapp265/7to1/basic_design/vhdl/constraints/
xapp265/7to1/basic_design/vhdl/constraints/top4_2v1000_fg456.ucf
xapp265/7to1/basic_design/vhdl/constraints/top8_2v1000_fg456.ucf
xapp265/7to1/basic_design/vhdl/design_files/
xapp265/7to1/basic_design/vhdl/design_files/m2_1p.vhd
xapp265/7to1/basic_design/vhdl/design_files/mux2_1.vhd
xapp265/7to1/basic_design/vhdl/design_files/serdes_4b_1to7.vhd
xapp265/7to1/basic_design/vhdl/design_files/serdes_4b_1to7_wrapper.vhd
xapp265/7to1/basic_design/vhdl/design_files/serdes_4b_1to7_wrapper_286.vhd
xapp265/7to1/basic_design/vhdl/design_files/serdes_4b_7to1.vhd
xapp265/7to1/basic_design/vhdl/design_files/serdes_4b_7to1_wrapper.vhd
xapp265/7to1/basic_design/vhdl/design_files/serdes_4b_7to1_wrapper_285.vhd
xapp265/7to1/basic_design/vhdl/design_files/serdes_8b_1to7_wrapper.vhd
xapp265/7to1/basic_design/vhdl/design_files/serdes_8b_1to7_wrapper_484.vhd
xapp265/7to1/basic_design/vhdl/design_files/serdes_8b_7to1_wrapper.vhd
xapp265/7to1/basic_design/vhdl/design_files/serdes_8b_7to1_wrapper_483.vhd
xapp265/7to1/basic_design/vhdl/design_files/top4.vhd
xapp265/7to1/basic_design/vhdl/design_files/top8.vhd
xapp265/7to1/basic_design/vhdl/simulation/
xapp265/7to1/basic_design/vhdl/simulation/tbtop4u.vhd
xapp265/7to1/basic

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