资源列表
huawei_shouce
- 华为技术有限公司的电器工程师手册包括硬件开发的基本过程和规范。-Huawei Technologies Co., Ltd. of electrical engineers manual includes hardware development process and the basic norms.
phpfreechat-1.0-beta6
- php Free Chat 是一个简单快捷和可自定义的聊天服务端,可以让站长们迅速构建自己的聊天室,并可以保存聊天记录,它使用AJAX技术,可以让聊天的页面过渡转换变得更亲切,它还支持CSS模版和插件系统. -php Free Chat is a simple, fast and can be obtained from the definition of the chat server, allows rapid construction of the station have their o
changyongdevhdl
- 4位乘法器,4位除法器 8位数据锁存器,8位相等比较器,带同步复位的状态 机,元件例化与层次设计,最高优先级编码器-four multipliers, dividers four eight data latches, and eight other phase comparators, synchronous reset with the state machine, the component level with the cases of design, the highest
ShiftRegister
- Structural Descr iption of an 8-bit Shift Register-Structural Descr iption of an 8-bit Shift R egister
LotteryNumberGenerator
- Lottery Number Generator的vhdl程序-Lottery Number Generator procedures for the vhdl
shuzilaozhong
- 该数字闹钟包括以下几个组成部分: (1) 显示屏,由6个七段数码管组成,用于显示当前时间(时 分 秒)或设置的闹钟时间 (2) KEY键:用于输入新的时间或新的闹钟时间时,对每位输入数字的确认 (3) TIME(时间)键,用于确定新的时间设置 (4) ALARM(闹钟)键,用于确定新的闹钟时间设置,或显示已设置的闹钟时间 (5) 扬声器,在当前时钟时间与闹钟时间时,发出蜂鸣声.-digital alarm clock, including the following components : (
banjiaqichengxu
- 用VHDL设计一个4位二进制并行半加器，要求将被加数、加数和加法运算和用动态扫描的方式共阴数码管一同时显示出-VHDL design a four-parallel binary adder, requesting summand, addends and multiplications and dynamic scanning of a total of Yam Digital also showed a
litianhua01
- 这是开发的管理系统很灵用你们首选试试看阿，很好用阿奥-This is a management system is very Ling use your preferred Try A good with Jo
dywl
- 大舜网络整站系统 v20060919-Da Shun entire network station system v20060919
sdgjv1.02
- 时代轨迹全站程序 v1.02-times the station's orbit procedures upscale
wjsclV1.2
- 无惧上传类 - UpFile_Class V1.2-without fear Upload category-UpFile_Class V1.2
wycq
- 无忧传奇私服下载站(带数据库)-worries legendary Download Station private servers (with database)