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文件名称:FPGA

  • 所属分类：
    Communication
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.9mb
  • 已下载：
    0次
  • 提 供 者：
    牟****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

FPGA编程课程演示PPT，包括语法入门，语法进阶和实例分析。-FPGA programming course presentation PPT, including Grammar, syntax and examples of advanced analysis.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

FPGA
FPGA/verilog
FPGA/verilog/1_060816185339
FPGA/verilog/1_060816185339/source
FPGA/verilog/1_060816185339/source/chap10
FPGA/verilog/1_060816185339/source/chap10/acc.acf
FPGA/verilog/1_060816185339/source/chap10/acc.hif
FPGA/verilog/1_060816185339/source/chap10/acc.v
FPGA/verilog/1_060816185339/source/chap10/accn.v
FPGA/verilog/1_060816185339/source/chap10/add8.v
FPGA/verilog/1_060816185339/source/chap10/adder8.v
FPGA/verilog/1_060816185339/source/chap10/block1.v
FPGA/verilog/1_060816185339/source/chap10/block2.v
FPGA/verilog/1_060816185339/source/chap10/block3.v
FPGA/verilog/1_060816185339/source/chap10/block4.v
FPGA/verilog/1_060816185339/source/chap10/control.v
FPGA/verilog/1_060816185339/source/chap10/fsm.v
FPGA/verilog/1_060816185339/source/chap10/longframe1.v
FPGA/verilog/1_060816185339/source/chap10/longframe2.v
FPGA/verilog/1_060816185339/source/chap10/pipeline.v
FPGA/verilog/1_060816185339/source/chap10/reg8.v
FPGA/verilog/1_060816185339/source/chap10/resource1.v
FPGA/verilog/1_060816185339/source/chap10/resource2.v
FPGA/verilog/1_060816185339/source/chap11
FPGA/verilog/1_060816185339/source/chap11/account.v
FPGA/verilog/1_060816185339/source/chap11/clock.v
FPGA/verilog/1_060816185339/source/chap11/count10.v
FPGA/verilog/1_060816185339/source/chap11/fre_ctrl.v
FPGA/verilog/1_060816185339/source/chap11/latch_16.v
FPGA/verilog/1_060816185339/source/chap11/paobiao.v
FPGA/verilog/1_060816185339/source/chap11/sell.v
FPGA/verilog/1_060816185339/source/chap11/song.v
FPGA/verilog/1_060816185339/source/chap11/traffic.v
FPGA/verilog/1_060816185339/source/chap12
FPGA/verilog/1_060816185339/source/chap12/add_ahead.v
FPGA/verilog/1_060816185339/source/chap12/add_bx.v
FPGA/verilog/1_060816185339/source/chap12/add_jl.v
FPGA/verilog/1_060816185339/source/chap12/add_tree.v
FPGA/verilog/1_060816185339/source/chap12/correlator.v
FPGA/verilog/1_060816185339/source/chap12/crc.v
FPGA/verilog/1_060816185339/source/chap12/cycle.v
FPGA/verilog/1_060816185339/source/chap12/decoder1.v
FPGA/verilog/1_060816185339/source/chap12/decoder2.v
FPGA/verilog/1_060816185339/source/chap12/fir.v
FPGA/verilog/1_060816185339/source/chap12/linear.v
FPGA/verilog/1_060816185339/source/chap12/mult.v
FPGA/verilog/1_060816185339/source/chap12/mult4x4.v
FPGA/verilog/1_060816185339/source/chap3
FPGA/verilog/1_060816185339/source/chap3/adder4.acf
FPGA/verilog/1_060816185339/source/chap3/adder4.hif
FPGA/verilog/1_060816185339/source/chap3/adder4.ndb
FPGA/verilog/1_060816185339/source/chap3/adder4.v
FPGA/verilog/1_060816185339/source/chap3/adder_tp.v
FPGA/verilog/1_060816185339/source/chap3/aoi.v
FPGA/verilog/1_060816185339/source/chap3/count4.v
FPGA/verilog/1_060816185339/source/chap3/count4_tp.v
FPGA/verilog/1_060816185339/source/chap5
FPGA/verilog/1_060816185339/source/chap5/adder.v
FPGA/verilog/1_060816185339/source/chap5/adder16.v
FPGA/verilog/1_060816185339/source/chap5/alu.v
FPGA/verilog/1_060816185339/source/chap5/block.v
FPGA/verilog/1_060816185339/source/chap5/buried_ff.v
FPGA/verilog/1_060816185339/source/chap5/compile.v
FPGA/verilog/1_060816185339/source/chap5/count.v
FPGA/verilog/1_060816185339/source/chap5/count60.v
FPGA/verilog/1_060816185339/source/chap5/decode4_7.v
FPGA/verilog/1_060816185339/source/chap5/loop1.v
FPGA/verilog/1_060816185339/source/chap5/loop2.v
FPGA/verilog/1_060816185339/source/chap5/loop3.v
FPGA/verilog/1_060816185339/source/chap5/mult_for.v
FPGA/verilog/1_060816185339/source/chap5/mult_repeat.v
FPGA/verilog/1_060816185339/source/chap5/mux21_1.v
FPGA/verilog/1_060816185339/source/chap5/mux21_2.v
FPGA/verilog/1_060816185339/source/chap5/mux4_1.v
FPGA/verilog/1_060816185339/source/chap5/mux_casez.v
FPGA/verilog/1_060816185339/source/chap5/non_block.v
FPGA/verilog/1_060816185339/source/chap5/test.v
FPGA/verilog/1_060816185339/source/chap5/voter7.v
FPGA/verilog/1_060816185339/source/chap5/wave1.v
FPGA/verilog/1_060816185339/source/chap5/wave2.v
FPGA/verilog/1_060816185339/source/chap6
FPGA/verilog/1_060816185339/source/chap6/alutask.v
FPGA/verilog/1_060816185339/source/chap6/alu_tp.v
FPGA/verilog/1_060816185339/source/chap6/code_83.v
FPGA/verilog/1_060816185339/source/chap6/count.v
FPGA/verilog/1_060816185339/source/chap6/funct.v
FPGA/verilog/1_060816185339/source/chap6/funct_tp.v
FPGA/verilog/1_060816185339/source/chap6/paral1.v
FPGA/verilog/1_060816185339/source/chap6/paral2.v
FPGA/verilog/1_060816185339/source/chap6/serial1.v
FPGA/verilog/1_060816185339/source/chap6/serial2.v
FPGA/verilog/1_060816185339/source/chap7
FPGA/verilog/1_060816185339/source/chap7/add4_1.v
FPGA/verilog/1_060816185339/source/chap7/add4_2.v
FPGA/verilog/1_060816185339/source/chap7/add4_3.v
FPGA/verilog/1_060816185339/source/chap7/count4.v
FPGA/verilog/1_060816185339/source/chap7/full_add1.v
FPGA/verilog/1_060816185339/source/chap7/full_add2.v
FPGA/verilog/1_060816185339/source/chap7/full_add3.v
FPGA/verilog/1_060816185339/source/chap7/full_add4.v
FPGA/verilog/1_060816185339/source/chap7/full_add5.v
FPGA/verilog/1_060816185339/source/chap7/half_add1.v
FPGA/verilog/1_060816185339/source/chap7/half_add2.v
FPGA/verilog/1_060816185339/source/chap7/half_add3.v
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