文件名称:verilog
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- 上传时间:2012-11-16
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文件大小:19.11mb
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大量verilog例程 详细具体 适合于初学者好好学习 -A large number of detailed and specific for verilog routine learn beginner
相关搜索: verilog
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下载文件列表
Verilog HDL程序设计/Chapter-1/adder/adder.cr.mti
Verilog HDL程序设计/Chapter-1/adder/adder.mpf
Verilog HDL程序设计/Chapter-1/adder/adder.v
Verilog HDL程序设计/Chapter-1/adder/adder_testbench.do
Verilog HDL程序设计/Chapter-1/adder/adder_testbench.v
Verilog HDL程序设计/Chapter-1/adder/chart/图1-3.bmp
Verilog HDL程序设计/Chapter-1/adder/chart/图1-4.bmp
Verilog HDL程序设计/Chapter-1/adder/chart/图1-5.bmp
Verilog HDL程序设计/Chapter-1/adder/chart/图1-6.bmp
Verilog HDL程序设计/Chapter-1/adder/chart/图1-7.bmp
Verilog HDL程序设计/Chapter-1/adder/chart/图1-8.bmp
Verilog HDL程序设计/Chapter-1/adder/transcript
Verilog HDL程序设计/Chapter-1/adder/vsim.wlf
Verilog HDL程序设计/Chapter-1/adder/work/adder/transcript
Verilog HDL程序设计/Chapter-1/adder/work/adder/verilog.txt.asm
Verilog HDL程序设计/Chapter-1/adder/work/adder/_primary.dat
Verilog HDL程序设计/Chapter-1/adder/work/adder/_primary.vhd
Verilog HDL程序设计/Chapter-1/adder/work/adder_testbench/verilog.asm
Verilog HDL程序设计/Chapter-1/adder/work/adder_testbench/_primary.dat
Verilog HDL程序设计/Chapter-1/adder/work/adder_testbench/_primary.vhd
Verilog HDL程序设计/Chapter-1/adder/work/_info
Verilog HDL程序设计/Chapter-10/10.2/chart/图10-12.bmp
Verilog HDL程序设计/Chapter-10/10.2/chart/图10-7.bmp
Verilog HDL程序设计/Chapter-10/10.2/chart/图10-8.bmp
Verilog HDL程序设计/Chapter-10/10.2/chart/图10-9.bmp
Verilog HDL程序设计/Chapter-10/10.2/csc.cr.mti
Verilog HDL程序设计/Chapter-10/10.2/csc.mpf
Verilog HDL程序设计/Chapter-10/10.2/csc_testbench.v
Verilog HDL程序设计/Chapter-10/10.2/rgb2ycrcb.v
Verilog HDL程序设计/Chapter-10/10.2/transcript
Verilog HDL程序设计/Chapter-10/10.2/vsim.wlf
Verilog HDL程序设计/Chapter-10/10.2/wave/csc_testbench.bmp
Verilog HDL程序设计/Chapter-10/10.2/wave/rgb2ycrcb.bmp
Verilog HDL程序设计/Chapter-10/10.2/work/csc_testbench/verilog.asm
Verilog HDL程序设计/Chapter-10/10.2/work/csc_testbench/_primary.dat
Verilog HDL程序设计/Chapter-10/10.2/work/csc_testbench/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.2/work/rgb2ycrcb/verilog.asm
Verilog HDL程序设计/Chapter-10/10.2/work/rgb2ycrcb/_primary.dat
Verilog HDL程序设计/Chapter-10/10.2/work/rgb2ycrcb/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.2/work/_info
Verilog HDL程序设计/Chapter-10/10.3/chart/图10-18.bmp
Verilog HDL程序设计/Chapter-10/10.3/chart/图10-19.bmp
Verilog HDL程序设计/Chapter-10/10.3/chart/图10-20.bmp
Verilog HDL程序设计/Chapter-10/10.3/chart/图10-22.bmp
Verilog HDL程序设计/Chapter-10/10.3/chart/图10-23.bmp
Verilog HDL程序设计/Chapter-10/10.3/chart/图10-25.bmp
Verilog HDL程序设计/Chapter-10/10.3/chart/图10-28.bmp
Verilog HDL程序设计/Chapter-10/10.3/chart/表10-3.bmp
Verilog HDL程序设计/Chapter-10/10.3/dct.cr.mti
Verilog HDL程序设计/Chapter-10/10.3/dct.mpf
Verilog HDL程序设计/Chapter-10/10.3/dct.v
Verilog HDL程序设计/Chapter-10/10.3/dctu.v
Verilog HDL程序设计/Chapter-10/10.3/dctub.v
Verilog HDL程序设计/Chapter-10/10.3/dct_cos_table.v
Verilog HDL程序设计/Chapter-10/10.3/dct_mac.v
Verilog HDL程序设计/Chapter-10/10.3/dct_syn.v
Verilog HDL程序设计/Chapter-10/10.3/dct_testbench.v
Verilog HDL程序设计/Chapter-10/10.3/fdct.v
Verilog HDL程序设计/Chapter-10/10.3/qnr.cr.mti
Verilog HDL程序设计/Chapter-10/10.3/timescale.v
Verilog HDL程序设计/Chapter-10/10.3/transcript
Verilog HDL程序设计/Chapter-10/10.3/vsim.wlf
Verilog HDL程序设计/Chapter-10/10.3/wave/dct.bmp
Verilog HDL程序设计/Chapter-10/10.3/wave/dctu.bmp
Verilog HDL程序设计/Chapter-10/10.3/wave/dctub.bmp
Verilog HDL程序设计/Chapter-10/10.3/wave/dct_testbench.bmp
Verilog HDL程序设计/Chapter-10/10.3/wave/fdct.bmp
Verilog HDL程序设计/Chapter-10/10.3/wave/zigzag.bmp
Verilog HDL程序设计/Chapter-10/10.3/work/bench_top/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/bench_top/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/bench_top/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/dct/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/dct/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/dct/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/dctu/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/dctu/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/dctu/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/dctub/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/dctub/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/dctub/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/dct_mac/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/dct_mac/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/dct_mac/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/dct_syn/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/dct_syn/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/dct_syn/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/dct_testbench/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/dct_testbench/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/dct_testbench/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/fdct/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/fdct/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/fdct/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/zigzag/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/zigzag/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/zigzag/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/_info
Verilog HDL程序设计/Chapter-10/10.3/zigzag.v
Verilog HDL程序设计/Chapter-10/10.4/bench_div_top.v
Verilog HDL程序设计/Chapter-10/10.4/bench_qnr_top.v
Verilog HDL程序设计/Chapter-10/10.4/chart/图10-32.bmp
Verilog HDL程序设计/Chapter-10/10.4/chart/图10-34.bmp
Ve
Verilog HDL程序设计/Chapter-1/adder/adder.mpf
Verilog HDL程序设计/Chapter-1/adder/adder.v
Verilog HDL程序设计/Chapter-1/adder/adder_testbench.do
Verilog HDL程序设计/Chapter-1/adder/adder_testbench.v
Verilog HDL程序设计/Chapter-1/adder/chart/图1-3.bmp
Verilog HDL程序设计/Chapter-1/adder/chart/图1-4.bmp
Verilog HDL程序设计/Chapter-1/adder/chart/图1-5.bmp
Verilog HDL程序设计/Chapter-1/adder/chart/图1-6.bmp
Verilog HDL程序设计/Chapter-1/adder/chart/图1-7.bmp
Verilog HDL程序设计/Chapter-1/adder/chart/图1-8.bmp
Verilog HDL程序设计/Chapter-1/adder/transcript
Verilog HDL程序设计/Chapter-1/adder/vsim.wlf
Verilog HDL程序设计/Chapter-1/adder/work/adder/transcript
Verilog HDL程序设计/Chapter-1/adder/work/adder/verilog.txt.asm
Verilog HDL程序设计/Chapter-1/adder/work/adder/_primary.dat
Verilog HDL程序设计/Chapter-1/adder/work/adder/_primary.vhd
Verilog HDL程序设计/Chapter-1/adder/work/adder_testbench/verilog.asm
Verilog HDL程序设计/Chapter-1/adder/work/adder_testbench/_primary.dat
Verilog HDL程序设计/Chapter-1/adder/work/adder_testbench/_primary.vhd
Verilog HDL程序设计/Chapter-1/adder/work/_info
Verilog HDL程序设计/Chapter-10/10.2/chart/图10-12.bmp
Verilog HDL程序设计/Chapter-10/10.2/chart/图10-7.bmp
Verilog HDL程序设计/Chapter-10/10.2/chart/图10-8.bmp
Verilog HDL程序设计/Chapter-10/10.2/chart/图10-9.bmp
Verilog HDL程序设计/Chapter-10/10.2/csc.cr.mti
Verilog HDL程序设计/Chapter-10/10.2/csc.mpf
Verilog HDL程序设计/Chapter-10/10.2/csc_testbench.v
Verilog HDL程序设计/Chapter-10/10.2/rgb2ycrcb.v
Verilog HDL程序设计/Chapter-10/10.2/transcript
Verilog HDL程序设计/Chapter-10/10.2/vsim.wlf
Verilog HDL程序设计/Chapter-10/10.2/wave/csc_testbench.bmp
Verilog HDL程序设计/Chapter-10/10.2/wave/rgb2ycrcb.bmp
Verilog HDL程序设计/Chapter-10/10.2/work/csc_testbench/verilog.asm
Verilog HDL程序设计/Chapter-10/10.2/work/csc_testbench/_primary.dat
Verilog HDL程序设计/Chapter-10/10.2/work/csc_testbench/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.2/work/rgb2ycrcb/verilog.asm
Verilog HDL程序设计/Chapter-10/10.2/work/rgb2ycrcb/_primary.dat
Verilog HDL程序设计/Chapter-10/10.2/work/rgb2ycrcb/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.2/work/_info
Verilog HDL程序设计/Chapter-10/10.3/chart/图10-18.bmp
Verilog HDL程序设计/Chapter-10/10.3/chart/图10-19.bmp
Verilog HDL程序设计/Chapter-10/10.3/chart/图10-20.bmp
Verilog HDL程序设计/Chapter-10/10.3/chart/图10-22.bmp
Verilog HDL程序设计/Chapter-10/10.3/chart/图10-23.bmp
Verilog HDL程序设计/Chapter-10/10.3/chart/图10-25.bmp
Verilog HDL程序设计/Chapter-10/10.3/chart/图10-28.bmp
Verilog HDL程序设计/Chapter-10/10.3/chart/表10-3.bmp
Verilog HDL程序设计/Chapter-10/10.3/dct.cr.mti
Verilog HDL程序设计/Chapter-10/10.3/dct.mpf
Verilog HDL程序设计/Chapter-10/10.3/dct.v
Verilog HDL程序设计/Chapter-10/10.3/dctu.v
Verilog HDL程序设计/Chapter-10/10.3/dctub.v
Verilog HDL程序设计/Chapter-10/10.3/dct_cos_table.v
Verilog HDL程序设计/Chapter-10/10.3/dct_mac.v
Verilog HDL程序设计/Chapter-10/10.3/dct_syn.v
Verilog HDL程序设计/Chapter-10/10.3/dct_testbench.v
Verilog HDL程序设计/Chapter-10/10.3/fdct.v
Verilog HDL程序设计/Chapter-10/10.3/qnr.cr.mti
Verilog HDL程序设计/Chapter-10/10.3/timescale.v
Verilog HDL程序设计/Chapter-10/10.3/transcript
Verilog HDL程序设计/Chapter-10/10.3/vsim.wlf
Verilog HDL程序设计/Chapter-10/10.3/wave/dct.bmp
Verilog HDL程序设计/Chapter-10/10.3/wave/dctu.bmp
Verilog HDL程序设计/Chapter-10/10.3/wave/dctub.bmp
Verilog HDL程序设计/Chapter-10/10.3/wave/dct_testbench.bmp
Verilog HDL程序设计/Chapter-10/10.3/wave/fdct.bmp
Verilog HDL程序设计/Chapter-10/10.3/wave/zigzag.bmp
Verilog HDL程序设计/Chapter-10/10.3/work/bench_top/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/bench_top/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/bench_top/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/dct/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/dct/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/dct/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/dctu/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/dctu/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/dctu/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/dctub/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/dctub/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/dctub/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/dct_mac/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/dct_mac/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/dct_mac/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/dct_syn/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/dct_syn/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/dct_syn/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/dct_testbench/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/dct_testbench/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/dct_testbench/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/fdct/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/fdct/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/fdct/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/zigzag/verilog.asm
Verilog HDL程序设计/Chapter-10/10.3/work/zigzag/_primary.dat
Verilog HDL程序设计/Chapter-10/10.3/work/zigzag/_primary.vhd
Verilog HDL程序设计/Chapter-10/10.3/work/_info
Verilog HDL程序设计/Chapter-10/10.3/zigzag.v
Verilog HDL程序设计/Chapter-10/10.4/bench_div_top.v
Verilog HDL程序设计/Chapter-10/10.4/bench_qnr_top.v
Verilog HDL程序设计/Chapter-10/10.4/chart/图10-32.bmp
Verilog HDL程序设计/Chapter-10/10.4/chart/图10-34.bmp
Ve
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