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文件名称:AlteraFPGACPLD

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    3.3mb
  • 已下载：
    0次
  • 提 供 者：
    天*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

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《ALTERA FPGA/CPLD 设计》附带光盘，内有书中案例的源代码及使用说明。-" ALTERA FPGA/CPLD Design"　with CD case containing the book' s source code and instructions.
相关搜索： altera FPGA cpld FPGA cpld

(系统自动生成,下载前可以参看下载内容)

下载文件列表

AlteraFPGACPLD设计/光盘使用说明.doc
AlteraFPGACPLD设计/Example-s6-1/示例说明.doc
AlteraFPGACPLD设计/Example-s6-1/Solution/debounce.bsf
AlteraFPGACPLD设计/Example-s6-1/Solution/debounce.v
AlteraFPGACPLD设计/Example-s6-1/Solution/defs.v
AlteraFPGACPLD设计/Example-s6-1/Solution/my_compare.bsf
AlteraFPGACPLD设计/Example-s6-1/Solution/my_compare.v
AlteraFPGACPLD设计/Example-s6-1/Solution/my_counter.bsf
AlteraFPGACPLD设计/Example-s6-1/Solution/my_counter.v
AlteraFPGACPLD设计/Example-s6-1/Solution/my_dff.bsf
AlteraFPGACPLD设计/Example-s6-1/Solution/my_dff.tdf
AlteraFPGACPLD设计/Example-s6-1/Solution/my_mux.bsf
AlteraFPGACPLD设计/Example-s6-1/Solution/my_mux.tdf
AlteraFPGACPLD设计/Example-s6-1/Solution/new_project.tcl
AlteraFPGACPLD设计/Example-s6-1/Solution/report_failing.tcl
AlteraFPGACPLD设计/Example-s6-1/Solution/svnseg.bsf
AlteraFPGACPLD设计/Example-s6-1/Solution/svnseg.tdf
AlteraFPGACPLD设计/Example-s6-1/Solution/tictactoe.bsf
AlteraFPGACPLD设计/Example-s6-1/Solution/tictactoe.v
AlteraFPGACPLD设计/Example-s6-1/Solution/top.bdf
AlteraFPGACPLD设计/Example-s6-1/Solution/命令行说明.txt
AlteraFPGACPLD设计/Example-s6-1/Project/debounce.bsf
AlteraFPGACPLD设计/Example-s6-1/Project/debounce.v
AlteraFPGACPLD设计/Example-s6-1/Project/defs.v
AlteraFPGACPLD设计/Example-s6-1/Project/my_compare.bsf
AlteraFPGACPLD设计/Example-s6-1/Project/my_compare.v
AlteraFPGACPLD设计/Example-s6-1/Project/my_counter.bsf
AlteraFPGACPLD设计/Example-s6-1/Project/my_counter.v
AlteraFPGACPLD设计/Example-s6-1/Project/my_dff.bsf
AlteraFPGACPLD设计/Example-s6-1/Project/my_dff.tdf
AlteraFPGACPLD设计/Example-s6-1/Project/my_mux.bsf
AlteraFPGACPLD设计/Example-s6-1/Project/my_mux.tdf
AlteraFPGACPLD设计/Example-s6-1/Project/new_project.tcl
AlteraFPGACPLD设计/Example-s6-1/Project/report_failing.tcl
AlteraFPGACPLD设计/Example-s6-1/Project/svnseg.bsf
AlteraFPGACPLD设计/Example-s6-1/Project/svnseg.tdf
AlteraFPGACPLD设计/Example-s6-1/Project/tictactoe.bsf
AlteraFPGACPLD设计/Example-s6-1/Project/tictactoe.v
AlteraFPGACPLD设计/Example-s6-1/Project/top.bdf
AlteraFPGACPLD设计/Example-s5-1/示例说明.doc
AlteraFPGACPLD设计/Example-s5-1/source/perf_opt/des.v
AlteraFPGACPLD设计/Example-s5-1/source/perf_opt/key_sel.v
AlteraFPGACPLD设计/Example-s5-1/source/common/crp.v
AlteraFPGACPLD设计/Example-s5-1/source/common/sbox1.v
AlteraFPGACPLD设计/Example-s5-1/source/common/sbox2.v
AlteraFPGACPLD设计/Example-s5-1/source/common/sbox3.v
AlteraFPGACPLD设计/Example-s5-1/source/common/sbox4.v
AlteraFPGACPLD设计/Example-s5-1/source/common/sbox5.v
AlteraFPGACPLD设计/Example-s5-1/source/common/sbox6.v
AlteraFPGACPLD设计/Example-s5-1/source/common/sbox7.v
AlteraFPGACPLD设计/Example-s5-1/source/common/sbox8.v
AlteraFPGACPLD设计/Example-s5-1/source/area_opt/des.v
AlteraFPGACPLD设计/Example-s5-1/source/area_opt/key_sel.v
AlteraFPGACPLD设计/Example-s5-1/des/cmp_state.ini
AlteraFPGACPLD设计/Example-s5-1/des/des.qpf
AlteraFPGACPLD设计/Example-s5-1/des/des.qsf
AlteraFPGACPLD设计/Example-s5-1/des/des.qws
AlteraFPGACPLD设计/Example-s5-1/des/des.ssf
AlteraFPGACPLD设计/Example-s5-1/des/des.vqm
AlteraFPGACPLD设计/Example-s5-1/des/des.bak/des.ssf
AlteraFPGACPLD设计/Example-s5-1/des/db/des.db_info
AlteraFPGACPLD设计/Example-s5-1/des/db/des.project.hdb
AlteraFPGACPLD设计/Example-s3-1/示例说明.doc
AlteraFPGACPLD设计/Example-s3-1/LogicLock/cmp_state.ini
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir_top.bsf
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir_top_coef_0.mif
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir_top_coef_1.mif
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir_top_coef_2.mif
AlteraFPGACPLD设计/Example-s3-1/LogicLock/lockit.asm.rpt
AlteraFPGACPLD设计/Example-s3-1/LogicLock/lockit.bdf
AlteraFPGACPLD设计/Example-s3-1/LogicLock/lockit.done
AlteraFPGACPLD设计/Example-s3-1/LogicLock/lockit.fit.eqn
AlteraFPGACPLD设计/Example-s3-1/LogicLock/lockit.fit.rpt
AlteraFPGACPLD设计/Example-s3-1/LogicLock/lockit.fld
AlteraFPGACPLD设计/Example-s3-1/LogicLock/lockit.flow.rpt
AlteraFPGACPLD设计/Example-s3-1/LogicLock/lockit.map.eqn
AlteraFPGACPLD设计/Example-s3-1/LogicLock/lockit.map.rpt
AlteraFPGACPLD设计/Example-s3-1/LogicLock/lockit.pin
AlteraFPGACPLD设计/Example-s3-1/LogicLock/lockit.qpf
AlteraFPGACPLD设计/Example-s3-1/LogicLock/lockit.qsf
AlteraFPGACPLD设计/Example-s3-1/LogicLock/lockit.qws
AlteraFPGACPLD设计/Example-s3-1/LogicLock/lockit.tan.rpt
AlteraFPGACPLD设计/Example-s3-1/LogicLock/lockit.tan.summary
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir/coef_log.txt
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir/coef_param.txt
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir/fir_top.asm.rpt
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir/fir_top.bsf
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir/fir_top.cmp
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir/fir_top.done
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir/fir_top.fit.eqn
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir/fir_top.fit.rpt
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir/fir_top.fld
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir/fir_top.flow.rpt
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir/fir_top.inc
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir/fir_top.map.eqn
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir/fir_top.map.rpt
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir/fir_top.pin
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir/fir_top.pof
AlteraFPGACPLD设计/Example-s3-1/LogicLock/fir/fir_

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