文件名称:i2c(FPGA)
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基于FPGA的I2C总线模拟,采用verilog HDL语言编写。-FPGA-based I2C bus simulation, using verilog HDL language.
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下载文件列表
I2C
I2C/I2C.dhp
I2C/I2C.npl
I2C/__projnav.log
I2C/automake.log
I2C/coregen.log
I2C/coregen.prj
I2C/i2c_master_bit_ctrl.cmd_log
I2C/i2c_master_bit_ctrl.lso
I2C/i2c_master_bit_ctrl.ngc
I2C/i2c_master_bit_ctrl.ngr
I2C/i2c_master_bit_ctrl.prj
I2C/i2c_master_bit_ctrl.stx
I2C/i2c_master_bit_ctrl.syr
I2C/i2c_master_bit_ctrl.v
I2C/i2c_master_bit_ctrl.v.bak
I2C/i2c_master_bit_ctrl_vhdl.prj
I2C/i2c_master_byte_ctrl.cmd_log
I2C/i2c_master_byte_ctrl.lso
I2C/i2c_master_byte_ctrl.ngc
I2C/i2c_master_byte_ctrl.ngr
I2C/i2c_master_byte_ctrl.prj
I2C/i2c_master_byte_ctrl.stx
I2C/i2c_master_byte_ctrl.syr
I2C/i2c_master_byte_ctrl.v
I2C/i2c_master_byte_ctrl.v.bak
I2C/i2c_master_byte_ctrl_vhdl.prj
I2C/i2c_master_defines.v
I2C/i2c_master_defines.v.bak
I2C/i2c_master_top.cmd_log
I2C/i2c_master_top.lso
I2C/i2c_master_top.ngc
I2C/i2c_master_top.ngr
I2C/i2c_master_top.prj
I2C/i2c_master_top.stx
I2C/i2c_master_top.syr
I2C/i2c_master_top.v
I2C/i2c_master_top.v.bak
I2C/i2c_master_top_vhdl.prj
I2C/i2c_slave_model.fdo
I2C/i2c_slave_model.ndo
I2C/i2c_slave_model.udo
I2C/i2c_slave_model.v
I2C/i2c_slave_model.v.bak
I2C/prjname.lso
I2C/timescale.v
I2C/transcript
I2C/tst_bench_top.v
I2C/wb_master_model.v
I2C/wb_master_model.v.bak
I2C/xst
I2C/xst/work
I2C/xst/work/hdllib.ref
I2C/xst/work/vlg67
I2C/xst/work/vlg67/i2c_master_top.bin
I2C/xst/work/vlg5C
I2C/xst/work/vlg5C/i2c_master_byte_ctrl.bin
I2C/xst/work/vlg07
I2C/xst/work/vlg07/i2c_master_bit_ctrl.bin
I2C/work
I2C/work/_info
I2C/work/i2c_slave_model
I2C/work/i2c_slave_model/_primary.dat
I2C/work/i2c_slave_model/_primary.vhd
I2C/work/i2c_slave_model/verilog.asm
I2C/work/glbl
I2C/work/glbl/_primary.dat
I2C/work/glbl/_primary.vhd
I2C/work/glbl/verilog.asm
I2C/__projnav
I2C/__projnav/I2C.gfl
I2C/__projnav/I2C_flowplus.gfl
I2C/__projnav/coregen.rsp
I2C/__projnav/i2c_master_bit_ctrl.xst
I2C/__projnav/i2c_master_byte_ctrl.xst
I2C/__projnav/i2c_master_top.xst
I2C/__projnav/runXst_tcl.rsp
I2C/__projnav/xst_sprjTOstx_tcl.rsp
www.dssz.com.txt
I2C/I2C.dhp
I2C/I2C.npl
I2C/__projnav.log
I2C/automake.log
I2C/coregen.log
I2C/coregen.prj
I2C/i2c_master_bit_ctrl.cmd_log
I2C/i2c_master_bit_ctrl.lso
I2C/i2c_master_bit_ctrl.ngc
I2C/i2c_master_bit_ctrl.ngr
I2C/i2c_master_bit_ctrl.prj
I2C/i2c_master_bit_ctrl.stx
I2C/i2c_master_bit_ctrl.syr
I2C/i2c_master_bit_ctrl.v
I2C/i2c_master_bit_ctrl.v.bak
I2C/i2c_master_bit_ctrl_vhdl.prj
I2C/i2c_master_byte_ctrl.cmd_log
I2C/i2c_master_byte_ctrl.lso
I2C/i2c_master_byte_ctrl.ngc
I2C/i2c_master_byte_ctrl.ngr
I2C/i2c_master_byte_ctrl.prj
I2C/i2c_master_byte_ctrl.stx
I2C/i2c_master_byte_ctrl.syr
I2C/i2c_master_byte_ctrl.v
I2C/i2c_master_byte_ctrl.v.bak
I2C/i2c_master_byte_ctrl_vhdl.prj
I2C/i2c_master_defines.v
I2C/i2c_master_defines.v.bak
I2C/i2c_master_top.cmd_log
I2C/i2c_master_top.lso
I2C/i2c_master_top.ngc
I2C/i2c_master_top.ngr
I2C/i2c_master_top.prj
I2C/i2c_master_top.stx
I2C/i2c_master_top.syr
I2C/i2c_master_top.v
I2C/i2c_master_top.v.bak
I2C/i2c_master_top_vhdl.prj
I2C/i2c_slave_model.fdo
I2C/i2c_slave_model.ndo
I2C/i2c_slave_model.udo
I2C/i2c_slave_model.v
I2C/i2c_slave_model.v.bak
I2C/prjname.lso
I2C/timescale.v
I2C/transcript
I2C/tst_bench_top.v
I2C/wb_master_model.v
I2C/wb_master_model.v.bak
I2C/xst
I2C/xst/work
I2C/xst/work/hdllib.ref
I2C/xst/work/vlg67
I2C/xst/work/vlg67/i2c_master_top.bin
I2C/xst/work/vlg5C
I2C/xst/work/vlg5C/i2c_master_byte_ctrl.bin
I2C/xst/work/vlg07
I2C/xst/work/vlg07/i2c_master_bit_ctrl.bin
I2C/work
I2C/work/_info
I2C/work/i2c_slave_model
I2C/work/i2c_slave_model/_primary.dat
I2C/work/i2c_slave_model/_primary.vhd
I2C/work/i2c_slave_model/verilog.asm
I2C/work/glbl
I2C/work/glbl/_primary.dat
I2C/work/glbl/_primary.vhd
I2C/work/glbl/verilog.asm
I2C/__projnav
I2C/__projnav/I2C.gfl
I2C/__projnav/I2C_flowplus.gfl
I2C/__projnav/coregen.rsp
I2C/__projnav/i2c_master_bit_ctrl.xst
I2C/__projnav/i2c_master_byte_ctrl.xst
I2C/__projnav/i2c_master_top.xst
I2C/__projnav/runXst_tcl.rsp
I2C/__projnav/xst_sprjTOstx_tcl.rsp
www.dssz.com.txt
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