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文件名称:UART

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  • 上传时间:
    2012-11-16
  • 文件大小:
    9.54mb
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    0次
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    别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容来自于网络,使用问题请自行百度

串行接口芯片的设计。本程序是在ISE开发环境中编写的UART串行通信接口。适合初学者的学习。-Serial interface chip designs. The program is written in the ISE development environment in the UART serial communication interface. For beginners to learn.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

UART/UART.ise
UART/__ISE_repository_UART.ise_.lock
UART/UART.restore
UART/parity_verifier.prj
UART/parity_verifier.xst
UART/parity_verifier.stx
UART/.lso
UART/shift_reg.prj
UART/_xmsgs/ngdbuild.xmsgs
UART/_xmsgs/map.xmsgs
UART/_xmsgs/par.xmsgs
UART/_xmsgs/trce.xmsgs
UART/_xmsgs/netgen.xmsgs
UART/_xmsgs/bitgen.xmsgs
UART/_xmsgs/xst.xmsgs
UART/_xmsgs/fuse.xmsgs
UART/UART.ise_ISE_Backup
UART/shift_reg.xst
UART/shift_reg.stx
UART/switcher_bus.prj
UART/switcher_bus.xst
UART/switcher_bus.stx
UART/uart_core.prj
UART/uart_core.xst
UART/uart_core.stx
UART/uart_top.v
UART/uart_top_summary.html
UART/uart_top.prj
UART/uart_top.xst
UART/uart_top.stx
UART/test_uart_v.v
UART/test_uart_v_summary.html
UART/test_uart_v.prj
UART/test_uart_v.xst
UART/test_uart_v.stx
UART/xilinxsim.ini
UART/test_uart_v_stx.prj
UART/isim/temp/vlg24/uart__core.bin
UART/isim/temp/hdllib.ref
UART/isim/temp/vlg62/switcher__bus.bin
UART/isim/temp/vlg43/shift__reg.bin
UART/isim/temp/vlg64/parity__verifier.bin
UART/isim/temp/vlg02/detector.bin
UART/isim/temp/vlg10/counter.bin
UART/isim/temp/vlg16/baudrate__generator.bin
UART/isim/temp/vlg1A/uart__top.bin
UART/isim/temp/vlg54/test__uart__v.bin
UART/isim/temp/vlg2D/glbl.bin
UART/isim/temp/vlg7E/test1__v.bin
UART/isim/temp/vlg17/test2__v.bin
UART/isim/temp/vlg30/test3__v.bin
UART/isim/temp/hdpdeps.ref
UART/isim/work/vlg24/uart__core.bin
UART/isim/work/hdllib.ref
UART/isim/work/uart__core/uart__core.h
UART/isim/work/uart__core/mingw/uart__core.obj
UART/isim/work/vlg62/switcher__bus.bin
UART/isim/work/switcher__bus/switcher__bus.h
UART/isim/work/switcher__bus/mingw/switcher__bus.obj
UART/isim/work/vlg43/shift__reg.bin
UART/isim/work/shift__reg/shift__reg.h
UART/isim/work/shift__reg/mingw/shift__reg.obj
UART/isim/work/vlg64/parity__verifier.bin
UART/isim/work/parity__verifier/parity__verifier.h
UART/isim/work/parity__verifier/mingw/parity__verifier.obj
UART/isim/work/vlg02/detector.bin
UART/isim/work/detector/detector.h
UART/isim/work/detector/mingw/detector.obj
UART/isim/work/detector/xsimdetector.cpp
UART/isim/work/vlg10/counter.bin
UART/isim/work/counter/counter.h
UART/isim/work/counter/mingw/counter.obj
UART/isim/work/counter/xsimcounter.cpp
UART/isim/work/vlg16/baudrate__generator.bin
UART/isim/work/baudrate__generator/baudrate__generator.h
UART/isim/work/baudrate__generator/mingw/baudrate__generator.obj
UART/isim/work/baudrate__generator/xsimbaudrate__generator.cpp
UART/isim/work/vlg1A/uart__top.bin
UART/isim/work/uart__top/uart__top.h
UART/isim/work/uart__top/mingw/uart__top.obj
UART/isim/work/uart__top/xsimuart__top.cpp
UART/isim/work/vlg54/test__uart__v.bin
UART/isim/work/test__uart__v/test__uart__v.h
UART/isim/work/test__uart__v/mingw/test__uart__v.obj
UART/isim/work/test__uart__v/xsimtest__uart__v.cpp
UART/isim/work/vlg2D/glbl.bin
UART/isim/work/glbl/glbl.h
UART/isim/work/glbl/mingw/glbl.obj
UART/isim/work/vlg7E/test1__v.bin
UART/isim/work/test1__v/test1__v.h
UART/isim/work/test1__v/mingw/test1__v.obj
UART/isim/work/test1__v/xsimtest1__v.cpp
UART/isim/work/vlg17/test2__v.bin
UART/isim/work/test2__v/test2__v.h
UART/isim/work/test2__v/mingw/test2__v.obj
UART/isim/work/test2__v/xsimtest2__v.cpp
UART/isim/work/vlg30/test3__v.bin
UART/isim/work/test3__v/test3__v.h
UART/isim/work/test3__v/mingw/test3__v.obj
UART/isim/work/test3__v/xsimtest3__v.cpp
UART/isim/work/hdpdeps.ref
UART/isim.hdlsourcefiles
UART/test_uart_v_isim_beh.exe
UART/isim.cmd
UART/isim.log
UART/isimwavedata.xwv
UART/detector_stx.prj
UART/isim.tmp_save/_1
UART/simulate_dofile.log
UART/uart_top_stx.prj
UART/simulate_dofile.log_back
UART/test_uart_v_isim_beh.wfs
UART/uart_top.lso
UART/detector.v
UART/test_bencher.prj
UART/test.xwv_bak
UART/test.ant
UART/test.jhd
UART/counter_isim_beh.wfs
UART/uart_top_isim_beh.wfs
UART/detector_beh.prj
UART/detector_isim_beh.exe
UART/detector_isim_beh.wfs
UART/uart_top.syr
UART/baudrate_generator_isim_beh.wfs
UART/uart_top.cmd_log
UART/UART.ntrc_log
UART/netgen/synthesis/uart_top_synthesis.nlf
UART/netgen/synthesis/uart_top_synthesis.v
UART/netgen/translate/uart_top_translate.nlf
UART/netgen/translate/uart_top_translate.v
UART/netgen/map/uart_top_map.nlf
UART/netgen/map/uart_top_map.sdf
UART/netgen/map/uart_top_map.v
UART/netgen/par/uart_top_timesim.nlf
UART/netgen/par/uart_top_timesim.sdf
UART/netgen/par/uart_top_timesim.v
UART/_ngo/netlist.lst
UART/uart_top.bld
UART/uart_top.ngr
UART/uart_top.ngc
UART/uart_top.ngd
UART/uart_top_prev_built.ngd
UART/uart_top_map.mrp
UART/uart_top_map.map
UART/uart_top_map.ngm
UART/uart_top.pcf
UART/uart_top_map.ncd
UART/uart_top_usage.xml
UART/uart_top_summary.xml
UART/uart_top_preroute.twx
UART/uart_top_preroute.twr
UART/uart_top.par
UART/uart_top.ncd
UART/uart_top.xpi
UART/uart_top_pad.csv
UART/uart_top.pad
UART/uart_top_pad.txt
UART/uart_top.unroutes
UART/uart_top_guide.ncd
UART/uart_top.twx
UART/uart_top.twr
UART/uart_top.ut
UART/uart_top.bgn
UART/uart_top.drc
UART/uart_top.bit
UART/device_usage_statistics.html
UART/_impact.cmd
UART/_impact.log
UART/test1_v_stx.prj
UART/test2_v_isim_beh.wfs
UART/test1_v_isim_beh.wfs
UART/test2_v_stx.prj
UART/test1_v_isim_beh.exe
UART/test1_v_summary.html

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