文件名称:dct
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- 上传时间:2012-11-16
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文件大小:102.68kb
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DCT的FPGA实现,用verilog语言把DCT的快速算法即LOEFFLER算法表示出来。-DCT-FPGA, with the verilog language to the fast DCT algorithm, which is LOEFFLER algorithm that out.
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下载文件列表
dct/automake.log
dct/coregen.log
dct/coregen.prj
dct/dct.cmd_log
dct/dct.dhp
dct/dct.lso
dct/dct.ngc
dct/dct.ngr
dct/dct.npl
dct/dct.prj
dct/dct.stx
dct/dct.syr
dct/dct.v
dct/dct_dct_t2_v_tf.fdo
dct/dct_dct_t2_v_tf.udo
dct/dct_t2.v
dct/dct_vhdl.prj
dct/multiplier.cmd_log
dct/multiplier.lso
dct/multiplier.ngc
dct/multiplier.ngr
dct/multiplier.prj
dct/multiplier.stx
dct/multiplier.syr
dct/multiplier_vhdl.prj
dct/transcript
dct/vsim.wlf
dct/work/dct/verilog.asm
dct/work/dct/_primary.dat
dct/work/dct/_primary.vhd
dct/work/dct
dct/work/dct_dct_t2_v_tf/verilog.asm
dct/work/dct_dct_t2_v_tf/_primary.dat
dct/work/dct_dct_t2_v_tf/_primary.vhd
dct/work/dct_dct_t2_v_tf
dct/work/dct_dct_t3_v_tf/verilog.asm
dct/work/dct_dct_t3_v_tf/_primary.dat
dct/work/dct_dct_t3_v_tf/_primary.vhd
dct/work/dct_dct_t3_v_tf
dct/work/dct_dct_t_v_tf/verilog.asm
dct/work/dct_dct_t_v_tf/_primary.dat
dct/work/dct_dct_t_v_tf/_primary.vhd
dct/work/dct_dct_t_v_tf
dct/work/glbl/verilog.asm
dct/work/glbl/_primary.dat
dct/work/glbl/_primary.vhd
dct/work/glbl
dct/work/multiplier/verilog.asm
dct/work/multiplier/_primary.dat
dct/work/multiplier/_primary.vhd
dct/work/multiplier
dct/work/_info
dct/work
dct/xst/work/hdllib.ref
dct/xst/work/vlg27/dct.bin
dct/xst/work/vlg27
dct/xst/work/vlg7B/multiplier.bin
dct/xst/work/vlg7B
dct/xst/work
dct/xst
dct/__projnav/coregen.rsp
dct/__projnav/createTF.err
dct/__projnav/dct.gfl
dct/__projnav/dct.xst
dct/__projnav/dct_flowplus.gfl
dct/__projnav/multiplier.xst
dct/__projnav/runXst_tcl.rsp
dct/__projnav
dct/__projnav.log
dct
dct/coregen.log
dct/coregen.prj
dct/dct.cmd_log
dct/dct.dhp
dct/dct.lso
dct/dct.ngc
dct/dct.ngr
dct/dct.npl
dct/dct.prj
dct/dct.stx
dct/dct.syr
dct/dct.v
dct/dct_dct_t2_v_tf.fdo
dct/dct_dct_t2_v_tf.udo
dct/dct_t2.v
dct/dct_vhdl.prj
dct/multiplier.cmd_log
dct/multiplier.lso
dct/multiplier.ngc
dct/multiplier.ngr
dct/multiplier.prj
dct/multiplier.stx
dct/multiplier.syr
dct/multiplier_vhdl.prj
dct/transcript
dct/vsim.wlf
dct/work/dct/verilog.asm
dct/work/dct/_primary.dat
dct/work/dct/_primary.vhd
dct/work/dct
dct/work/dct_dct_t2_v_tf/verilog.asm
dct/work/dct_dct_t2_v_tf/_primary.dat
dct/work/dct_dct_t2_v_tf/_primary.vhd
dct/work/dct_dct_t2_v_tf
dct/work/dct_dct_t3_v_tf/verilog.asm
dct/work/dct_dct_t3_v_tf/_primary.dat
dct/work/dct_dct_t3_v_tf/_primary.vhd
dct/work/dct_dct_t3_v_tf
dct/work/dct_dct_t_v_tf/verilog.asm
dct/work/dct_dct_t_v_tf/_primary.dat
dct/work/dct_dct_t_v_tf/_primary.vhd
dct/work/dct_dct_t_v_tf
dct/work/glbl/verilog.asm
dct/work/glbl/_primary.dat
dct/work/glbl/_primary.vhd
dct/work/glbl
dct/work/multiplier/verilog.asm
dct/work/multiplier/_primary.dat
dct/work/multiplier/_primary.vhd
dct/work/multiplier
dct/work/_info
dct/work
dct/xst/work/hdllib.ref
dct/xst/work/vlg27/dct.bin
dct/xst/work/vlg27
dct/xst/work/vlg7B/multiplier.bin
dct/xst/work/vlg7B
dct/xst/work
dct/xst
dct/__projnav/coregen.rsp
dct/__projnav/createTF.err
dct/__projnav/dct.gfl
dct/__projnav/dct.xst
dct/__projnav/dct_flowplus.gfl
dct/__projnav/multiplier.xst
dct/__projnav/runXst_tcl.rsp
dct/__projnav
dct/__projnav.log
dct
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