stc/designer/impl1/ada01988-3.tmp
stc/designer/impl1/ada01988-5.tmp
stc/designer/impl1/ada03856-1.tmp
stc/designer/impl1/ada03856-3.tmp
stc/designer/impl1/adder.ide_des
stc/designer/impl1/designer.log
stc/designer/impl1/designer_gen_ba.log
stc/designer/impl1/designer_synth_check.log
stc/designer/impl1/ram256.ide_des
stc/designer/impl1/read.ide_des
stc/designer/impl1/simulation/postlayout/testbench/verilog.psm
stc/designer/impl1/simulation/postlayout/testbench/_primary.dat
stc/designer/impl1/simulation/postlayout/testbench/_primary.dbs
stc/designer/impl1/simulation/postlayout/testbench/_primary.vhd
stc/designer/impl1/simulation/postlayout/top/verilog.psm
stc/designer/impl1/simulation/postlayout/top/_primary.dat
stc/designer/impl1/simulation/postlayout/top/_primary.dbs
stc/designer/impl1/simulation/postlayout/top/_primary.vhd
stc/designer/impl1/simulation/postlayout/_info
stc/designer/impl1/simulation/postlayout/_temp/vlog8hf1ct
stc/designer/impl1/simulation/postlayout/_temp/vloghh69wc
stc/designer/impl1/simulation/postlayout/_vmake
stc/designer/impl1/testbench.ide_des
stc/designer/impl1/top.adb
stc/designer/impl1/top.dtf/verify.log
stc/designer/impl1/top.ide_des
stc/designer/impl1/top.pdb
stc/designer/impl1/top.pdb.depends
stc/designer/impl1/top.tcl
stc/designer/impl1/top_1.adb
stc/designer/impl1/top_1.dtf/verify.log
stc/designer/impl1/top_1.ide_des
stc/designer/impl1/top_1.pdb
stc/designer/impl1/top_1.pdb.depends
stc/designer/impl1/top_1_ba.sdf
stc/designer/impl1/top_1_ba.v
stc/designer/impl1/top_1_fp/$$FlashPro_09421.L$$
stc/designer/impl1/top_1_fp/projectData/top_1.pdb
stc/designer/impl1/top_1_fp/top_1.log
stc/designer/impl1/top_1_fp/top_1.pro
stc/designer/impl1/top_2.adb
stc/designer/impl1/top_2.dtf/verify.log
stc/designer/impl1/top_2.ide_des
stc/designer/impl1/top_2.pdb
stc/designer/impl1/top_2.pdb.depends
stc/designer/impl1/top_2_ba.sdf
stc/designer/impl1/top_2_ba.sdf_max.csd
stc/designer/impl1/top_2_ba.v
stc/designer/impl1/top_ba.sdf
stc/designer/impl1/top_ba.sdf_max.csd
stc/designer/impl1/top_ba.v
stc/designer/impl1/top_fp/$$FlashPro_09421.L$$
stc/designer/impl1/top_fp/$$FlashPro_09423.L$$
stc/designer/impl1/top_fp/$$FlashPro_FPBBALTLPT1.L$$
stc/designer/impl1/top_fp/projectData/top.pdb
stc/designer/impl1/top_fp/top.log
stc/designer/impl1/top_fp/top.pro
stc/designer/impl1/top_fp_1/$$FlashPro_09421.L$$
stc/designer/impl1/top_fp_1/projectData/top.pdb
stc/designer/impl1/top_fp_1/top.log
stc/designer/impl1/top_fp_1/top.pro
stc/designer/impl1/write2.ide_des
stc/hdl/adder.txt
stc/hdl/adder.v
stc/hdl/read.v
stc/hdl/test/testbench.v
stc/hdl/test/test_read.v
stc/hdl/test/test_write.v
stc/hdl/testbench.v
stc/hdl/top.v
stc/hdl/write2.v
stc/simulation/modelsim.ini
stc/simulation/modelsim.ini.sav
stc/simulation/modelsim.log
stc/simulation/postsynth/adder/verilog.psm
stc/simulation/postsynth/adder/_primary.dat
stc/simulation/postsynth/adder/_primary.dbs
stc/simulation/postsynth/adder/_primary.vhd
stc/simulation/postsynth/ram256/verilog.psm
stc/simulation/postsynth/ram256/_primary.dat
stc/simulation/postsynth/ram256/_primary.dbs
stc/simulation/postsynth/ram256/_primary.vhd
stc/simulation/postsynth/read/verilog.psm
stc/simulation/postsynth/read/_primary.dat
stc/simulation/postsynth/read/_primary.dbs
stc/simulation/postsynth/read/_primary.vhd
stc/simulation/postsynth/testbench/verilog.psm
stc/simulation/postsynth/testbench/_primary.dat
stc/simulation/postsynth/testbench/_primary.dbs
stc/simulation/postsynth/testbench/_primary.vhd
stc/simulation/postsynth/top/verilog.psm
stc/simulation/postsynth/top/_primary.dat
stc/simulation/postsynth/top/_primary.dbs
stc/simulation/postsynth/top/_primary.vhd
stc/simulation/postsynth/write2/verilog.psm
stc/simulation/postsynth/write2/_primary.dat
stc/simulation/postsynth/write2/_primary.dbs
stc/simulation/postsynth/write2/_primary.vhd
stc/simulation/postsynth/_info
stc/simulation/postsynth/_temp/vlogk1iaqw
stc/simulation/postsynth/_temp/vlogtz45g9
stc/simulation/postsynth/_vmake
stc/simulation/presynth/adder/verilog.psm
stc/simulation/presynth/adder/_primary.dat
stc/simulation/presynth/adder/_primary.dbs
stc/simulation/presynth/adder/_primary.vhd
stc/simulation/presynth/ram256/verilog.psm
stc/simulation/presynth/ram256/_primary.dat
stc/simulation/presynth/ram256/_primary.dbs
stc/simulation/presynth/ram256/_primary.vhd
stc/simulation/presynth/read/verilog.psm
stc/simulation/presynth/read/_primary.dat
stc/simulation/presynth/read/_primary.dbs
stc/simulation/presynth/read/_primary.vhd
stc/simulation/presynth/testbench/verilog.psm
stc/simulation/presynth/testbench/_primary.dat
stc/simulation/presynth/testbench/_primary.dbs
stc/simulation/presynth/testbench/_primary.vhd
stc/simulation/presynth/top/verilog.psm
stc/simulation/presynth/top/_primary.dat
stc/simulation/presynth/top/_primary.dbs
stc/simulation/presynth/top/_primary.vhd
stc/simulation/presynth/write2/verilog.psm
stc/simulation/presynth/write2/_primary.dat
stc/simulation/presynth/write2/_primary.dbs
stc/simulation/presynth/write2/_primary.vhd
stc/simulation/presynth/_info
stc/simulation/presynth/_vmake
stc/simulation/ram256_R0C0.mem
stc/simulatio