文件名称:simple_spi
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- 上传时间:2012-11-16
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文件大小:570.65kb
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complete spi core written in vhdl. its easy to use and can be configured to operate at various clock frequencies. tested on an ADC to verify the operation
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下载文件列表
simple_spi/
simple_spi/branches/
simple_spi/tags/
simple_spi/tags/initial/
simple_spi/tags/initial/rtl/
simple_spi/tags/initial/rtl/verilog/
simple_spi/tags/initial/rtl/verilog/fifo4.v
simple_spi/tags/initial/rtl/verilog/simple_spi_top.v
simple_spi/trunk/
simple_spi/trunk/bench/
simple_spi/trunk/bench/verilog/
simple_spi/trunk/bench/verilog/spi_slave_model.v
simple_spi/trunk/bench/verilog/tst_bench_top.v
simple_spi/trunk/bench/verilog/wb_master_model.v
simple_spi/trunk/doc/
simple_spi/trunk/doc/simple_spi.pdf
simple_spi/trunk/doc/src/
simple_spi/trunk/doc/src/simple_spi.doc
simple_spi/trunk/rtl/
simple_spi/trunk/rtl/verilog/
simple_spi/trunk/rtl/verilog/fifo4.v
simple_spi/trunk/rtl/verilog/simple_spi_top.v
simple_spi/trunk/sim/
simple_spi/trunk/sim/rtl_sim/
simple_spi/trunk/sim/rtl_sim/bin/
simple_spi/trunk/sim/rtl_sim/bin/Makefile
simple_spi/trunk/sim/rtl_sim/run/
simple_spi/trunk/sim/rtl_sim/run/Makefile
simple_spi/trunk/sim/rtl_sim/run/ncsim.log
simple_spi/trunk/sim/rtl_sim/run/ncvlog.log
simple_spi/trunk/sim/rtl_sim/run/ncwork/
simple_spi/trunk/sim/rtl_sim/run/ncwork/cds.lib
simple_spi/trunk/sim/rtl_sim/run/ncwork/hdl.var
simple_spi/trunk/sim/rtl_sim/run/ncwork/work/
simple_spi/trunk/sim/rtl_sim/run/ncwork/work/.cdsvmod
simple_spi/trunk/sim/rtl_sim/run/ncwork/work/.inca.db.135.linux
simple_spi/trunk/sim/rtl_sim/run/ncwork/work/.inca.db.148.lnx86
simple_spi/trunk/sim/rtl_sim/run/ncwork/work/inca.linux.135.pak
simple_spi/trunk/sim/rtl_sim/run/ncwork/work/inca.lnx86.148.pak
simple_spi/trunk/sim/rtl_sim/run/simvision.sv
simple_spi/trunk/sim/rtl_sim/run/stdout.log
simple_spi/trunk/sim/rtl_sim/run/waves/
simple_spi/trunk/sim/rtl_sim/run/waves/waves.do
simple_spi/web_uploads/
simple_spi/branches/
simple_spi/tags/
simple_spi/tags/initial/
simple_spi/tags/initial/rtl/
simple_spi/tags/initial/rtl/verilog/
simple_spi/tags/initial/rtl/verilog/fifo4.v
simple_spi/tags/initial/rtl/verilog/simple_spi_top.v
simple_spi/trunk/
simple_spi/trunk/bench/
simple_spi/trunk/bench/verilog/
simple_spi/trunk/bench/verilog/spi_slave_model.v
simple_spi/trunk/bench/verilog/tst_bench_top.v
simple_spi/trunk/bench/verilog/wb_master_model.v
simple_spi/trunk/doc/
simple_spi/trunk/doc/simple_spi.pdf
simple_spi/trunk/doc/src/
simple_spi/trunk/doc/src/simple_spi.doc
simple_spi/trunk/rtl/
simple_spi/trunk/rtl/verilog/
simple_spi/trunk/rtl/verilog/fifo4.v
simple_spi/trunk/rtl/verilog/simple_spi_top.v
simple_spi/trunk/sim/
simple_spi/trunk/sim/rtl_sim/
simple_spi/trunk/sim/rtl_sim/bin/
simple_spi/trunk/sim/rtl_sim/bin/Makefile
simple_spi/trunk/sim/rtl_sim/run/
simple_spi/trunk/sim/rtl_sim/run/Makefile
simple_spi/trunk/sim/rtl_sim/run/ncsim.log
simple_spi/trunk/sim/rtl_sim/run/ncvlog.log
simple_spi/trunk/sim/rtl_sim/run/ncwork/
simple_spi/trunk/sim/rtl_sim/run/ncwork/cds.lib
simple_spi/trunk/sim/rtl_sim/run/ncwork/hdl.var
simple_spi/trunk/sim/rtl_sim/run/ncwork/work/
simple_spi/trunk/sim/rtl_sim/run/ncwork/work/.cdsvmod
simple_spi/trunk/sim/rtl_sim/run/ncwork/work/.inca.db.135.linux
simple_spi/trunk/sim/rtl_sim/run/ncwork/work/.inca.db.148.lnx86
simple_spi/trunk/sim/rtl_sim/run/ncwork/work/inca.linux.135.pak
simple_spi/trunk/sim/rtl_sim/run/ncwork/work/inca.lnx86.148.pak
simple_spi/trunk/sim/rtl_sim/run/simvision.sv
simple_spi/trunk/sim/rtl_sim/run/stdout.log
simple_spi/trunk/sim/rtl_sim/run/waves/
simple_spi/trunk/sim/rtl_sim/run/waves/waves.do
simple_spi/web_uploads/
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