文件名称:Solutions
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- 上传时间：2012-11-16
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文件大小：7.04kb
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`timescale 1ns / 1ps
module AND_OR(INP, OUT1)
input [3:0] INP
output OUT1
wire SIG1, SIG2
MY_AND2 U0 (.A(INP[0]), .B(INP[1]), .C(SIG1))
MY_AND2 U1 (.A(INP[2]), .B(INP[3]), .C(SIG2))
MY_OR2 U2 (.A(SIG1), .B(SIG2), .C(OUT1))
endmodule-`timescale 1ns / 1ps
module AND_OR(INP, OUT1)
input [3:0] INP
output OUT1
wire SIG1, SIG2
MY_AND2 U0 (.A(INP[0]), .B(INP[1]), .C(SIG1))
MY_AND2 U1 (.A(INP[2]), .B(INP[3]), .C(SIG2))
MY_OR2 U2 (.A(SIG1), .B(SIG2), .C(OUT1))
endmodule
module AND_OR(INP, OUT1)
input [3:0] INP
output OUT1
wire SIG1, SIG2
MY_AND2 U0 (.A(INP[0]), .B(INP[1]), .C(SIG1))
MY_AND2 U1 (.A(INP[2]), .B(INP[3]), .C(SIG2))
MY_OR2 U2 (.A(SIG1), .B(SIG2), .C(OUT1))
endmodule-`timescale 1ns / 1ps
module AND_OR(INP, OUT1)
input [3:0] INP
output OUT1
wire SIG1, SIG2
MY_AND2 U0 (.A(INP[0]), .B(INP[1]), .C(SIG1))
MY_AND2 U1 (.A(INP[2]), .B(INP[3]), .C(SIG2))
MY_OR2 U2 (.A(SIG1), .B(SIG2), .C(OUT1))
endmodule
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Solutions/ADDR_CNTR.v
Solutions/AND_OR.v
Solutions/AND_OR_TB.v
Solutions/CLK_DIV.v
Solutions/LED_DRIVER.ucf
Solutions/LED_DRIVER.v
Solutions/MEM.v
Solutions/MY_AND2.v
Solutions/MY_CNTR.v
Solutions/MY_CNTR_TB.v
Solutions/MY_HEADER.txt
Solutions/MY_INPUT.txt
Solutions/MY_OR2.v
Solutions/SECURITY_1.v
Solutions/SECURITY_1_TB.v
Solutions/SP_RAM8x16.v
Solutions/SP_RAM8x16_TB.v
Solutions/SP_RAM8x16_TB_solution.v
Solutions
Solutions/AND_OR.v
Solutions/AND_OR_TB.v
Solutions/CLK_DIV.v
Solutions/LED_DRIVER.ucf
Solutions/LED_DRIVER.v
Solutions/MEM.v
Solutions/MY_AND2.v
Solutions/MY_CNTR.v
Solutions/MY_CNTR_TB.v
Solutions/MY_HEADER.txt
Solutions/MY_INPUT.txt
Solutions/MY_OR2.v
Solutions/SECURITY_1.v
Solutions/SECURITY_1_TB.v
Solutions/SP_RAM8x16.v
Solutions/SP_RAM8x16_TB.v
Solutions/SP_RAM8x16_TB_solution.v
Solutions
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