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文件名称:cout_asyn

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    2012-11-16
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    206.02kb
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基于verilog的计数器设计,本例程将实现四位异步二进制计数器的功能,同时给出了同步二进制计数器和同步十进制计数器的VerilogHDL程序-Verilog counter based design, this routine will achieve the functions of four asynchronous binary counter, synchronous binary counter is given and synchronous decimal counter VerilogHDL procedures
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下载文件列表

cout_asyn/
cout_asyn/component/
cout_asyn/constraint/
cout_asyn/coreconsole/
cout_asyn/cout_asyn.prj
cout_asyn/designer/
cout_asyn/designer/impl1/
cout_asyn/designer/impl1/cout_asyn.adb
cout_asyn/designer/impl1/cout_asyn.dtf/
cout_asyn/designer/impl1/cout_asyn.dtf/verify.log
cout_asyn/designer/impl1/cout_asyn.ide_des
cout_asyn/designer/impl1/cout_asyn.pdb
cout_asyn/designer/impl1/cout_asyn.pdb.depends
cout_asyn/designer/impl1/cout_asyn.tcl
cout_asyn/designer/impl1/cout_asyn_fp/
cout_asyn/designer/impl1/cout_asyn_fp/$$FlashPro_FPBBALTLPT1.L$$
cout_asyn/designer/impl1/cout_asyn_fp/cout_asyn.log
cout_asyn/designer/impl1/cout_asyn_fp/cout_asyn.pro
cout_asyn/designer/impl1/cout_asyn_fp/projectData/
cout_asyn/designer/impl1/cout_asyn_fp/projectData/cout_asyn.pdb
cout_asyn/designer/impl1/designer.log
cout_asyn/designer/impl1/simulation/
cout_asyn/hdl/
cout_asyn/hdl/clk_div.v
cout_asyn/hdl/cout_asyn.v
cout_asyn/phy_synthesis/
cout_asyn/simulation/
cout_asyn/simulation/modelsim.ini
cout_asyn/smartgen/
cout_asyn/smartgen/smartgen.aws
cout_asyn/stimulus/
cout_asyn/synthesis/
cout_asyn/synthesis/.recordref
cout_asyn/synthesis/backup/
cout_asyn/synthesis/coreip/
cout_asyn/synthesis/cout_asyn.areasrr
cout_asyn/synthesis/cout_asyn.edn
cout_asyn/synthesis/cout_asyn.map
cout_asyn/synthesis/cout_asyn.pdc
cout_asyn/synthesis/cout_asyn.sdf
cout_asyn/synthesis/cout_asyn.so
cout_asyn/synthesis/cout_asyn.srd
cout_asyn/synthesis/cout_asyn.srm
cout_asyn/synthesis/cout_asyn.srr
cout_asyn/synthesis/cout_asyn.srs
cout_asyn/synthesis/cout_asyn.szr
cout_asyn/synthesis/cout_asyn.tlg
cout_asyn/synthesis/cout_asyn_sdc.sdc
cout_asyn/synthesis/cout_asyn_syn.prj
cout_asyn/synthesis/run_options.txt
cout_asyn/synthesis/stdout.log
cout_asyn/synthesis/syntmp/
cout_asyn/synthesis/syntmp/cout_asyn.plg
cout_asyn/synthesis/traplog.tlg
cout_asyn/viewdraw/
cout_asyn/viewdraw/sch/
cout_asyn/viewdraw/sym/
cout_asyn/viewdraw/vf/
cout_asyn/viewdraw/vf/project.lst
cout_asyn/viewdraw/viewdraw.ini
cout_asyn/viewdraw/wir/

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