文件名称:allot
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- 上传时间:2012-11-16
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文件大小:126.1kb
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基于verilog的数据分配器的设计-数据分配是将公共数据线上的数据根据需要送到不同的通道上区,实现数据分配功能的逻辑电路称为数据分配器。-Verilog-based distributor of design data- the data is public data online distribution of the data sent to different channels as needed on areas of data distribution function of logic circuit known as the data distributor.
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下载文件列表
allot/
allot/allot.prj
allot/component/
allot/constraint/
allot/coreconsole/
allot/designer/
allot/designer/impl1/
allot/designer/impl1/allot.adb
allot/designer/impl1/allot.dtf/
allot/designer/impl1/allot.dtf/verify.log
allot/designer/impl1/allot.ide_des
allot/designer/impl1/allot.pdb
allot/designer/impl1/allot.pdb.depends
allot/designer/impl1/allot.tcl
allot/designer/impl1/allot_fp/
allot/designer/impl1/allot_fp/$$FlashPro_FPBBALTLPT1.L$$
allot/designer/impl1/allot_fp/allot.log
allot/designer/impl1/allot_fp/allot.pro
allot/designer/impl1/allot_fp/projectData/
allot/designer/impl1/allot_fp/projectData/allot.pdb
allot/designer/impl1/designer.log
allot/designer/impl1/simulation/
allot/hdl/
allot/hdl/allot.v
allot/phy_synthesis/
allot/simulation/
allot/simulation/modelsim.ini
allot/smartgen/
allot/smartgen/smartgen.aws
allot/stimulus/
allot/synthesis/
allot/synthesis/allot.areasrr
allot/synthesis/allot.edn
allot/synthesis/allot.map
allot/synthesis/allot.pdc
allot/synthesis/allot.sdf
allot/synthesis/allot.so
allot/synthesis/allot.srd
allot/synthesis/allot.srm
allot/synthesis/allot.srr
allot/synthesis/allot.srs
allot/synthesis/allot.szr
allot/synthesis/allot.tlg
allot/synthesis/allot_sdc.sdc
allot/synthesis/allot_syn.prj
allot/synthesis/backup/
allot/synthesis/coreip/
allot/synthesis/run_options.txt
allot/synthesis/stdout.log
allot/synthesis/syntmp/
allot/synthesis/syntmp/allot.plg
allot/viewdraw/
allot/viewdraw/sch/
allot/viewdraw/sym/
allot/viewdraw/vf/
allot/viewdraw/vf/project.lst
allot/viewdraw/viewdraw.ini
allot/viewdraw/wir/
allot/allot.prj
allot/component/
allot/constraint/
allot/coreconsole/
allot/designer/
allot/designer/impl1/
allot/designer/impl1/allot.adb
allot/designer/impl1/allot.dtf/
allot/designer/impl1/allot.dtf/verify.log
allot/designer/impl1/allot.ide_des
allot/designer/impl1/allot.pdb
allot/designer/impl1/allot.pdb.depends
allot/designer/impl1/allot.tcl
allot/designer/impl1/allot_fp/
allot/designer/impl1/allot_fp/$$FlashPro_FPBBALTLPT1.L$$
allot/designer/impl1/allot_fp/allot.log
allot/designer/impl1/allot_fp/allot.pro
allot/designer/impl1/allot_fp/projectData/
allot/designer/impl1/allot_fp/projectData/allot.pdb
allot/designer/impl1/designer.log
allot/designer/impl1/simulation/
allot/hdl/
allot/hdl/allot.v
allot/phy_synthesis/
allot/simulation/
allot/simulation/modelsim.ini
allot/smartgen/
allot/smartgen/smartgen.aws
allot/stimulus/
allot/synthesis/
allot/synthesis/allot.areasrr
allot/synthesis/allot.edn
allot/synthesis/allot.map
allot/synthesis/allot.pdc
allot/synthesis/allot.sdf
allot/synthesis/allot.so
allot/synthesis/allot.srd
allot/synthesis/allot.srm
allot/synthesis/allot.srr
allot/synthesis/allot.srs
allot/synthesis/allot.szr
allot/synthesis/allot.tlg
allot/synthesis/allot_sdc.sdc
allot/synthesis/allot_syn.prj
allot/synthesis/backup/
allot/synthesis/coreip/
allot/synthesis/run_options.txt
allot/synthesis/stdout.log
allot/synthesis/syntmp/
allot/synthesis/syntmp/allot.plg
allot/viewdraw/
allot/viewdraw/sch/
allot/viewdraw/sym/
allot/viewdraw/vf/
allot/viewdraw/vf/project.lst
allot/viewdraw/viewdraw.ini
allot/viewdraw/wir/
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