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文件名称:CALCULAT.ZIP

  • 所属分类：
    VHDL编程
  • 标签属性：
    [PDF]
  • 上传时间：
    2008-10-13
  • 文件大小：
    608.89kb
  • 已下载：
    0次
  • 提 供 者：
    沈****
  • 相关连接：
    无
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

verilog源码，可实现两位的加法器，在xillinx foundation 3.1下验证通过-verilog source, the two can achieve Adder, In xillinx foundation 3.1 certification through
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ALDEC.INI
ALDEC.LOG
BTI.INI
CALCULAT.PDF
CALCULAT/ADDER.ALR
CALCULAT/ADDER.ASX
CALCULAT/ADDER.BAK
CALCULAT/ADDER.EDF
CALCULAT/ADDER.ER
CALCULAT/ADDER.LOG
CALCULAT/ADDER.OPT
CALCULAT/ADDER.V
CALCULAT/CALCULA1.BSC
CALCULAT/CALCULA1.ERR
CALCULAT/CALCULA1.SCH
CALCULAT/CALCULAT.ALB
CALCULAT/CALCULAT.BIT
CALCULAT/CALCULAT.EDN
CALCULAT/CALCULAT.LL
CALCULAT/CALCULAT.PRJ
CALCULAT/CALCULAT.TVE
CALCULAT/CALCULAT.UCF
CALCULAT/DECODER10TO7.ALR
CALCULAT/DECODER10TO7.ASX
CALCULAT/DECODER10TO7.EDF
CALCULAT/DECODER10TO7.ER
CALCULAT/DECODER10TO7.LOG
CALCULAT/DECODER10TO7.OPT
CALCULAT/DECODER10TO7.V
CALCULAT/DPMCOMP.TMP/CHIPS/ADDER/ADDER.CST
CALCULAT/DPMCOMP.TMP/CHIPS/ADDER/ADDER.RPT
CALCULAT/DPMCOMP.TMP/CHIPS/ADDER/ADDER.WS
CALCULAT/DPMCOMP.TMP/CHIPS/ADDER_OPT/ADDER_OPT.CST
CALCULAT/DPMCOMP.TMP/CHIPS/ADDER_OPT/ADDER_OPT.RPT
CALCULAT/DPMCOMP.TMP/CHIPS/ADDER_OPT/ADDER_OPT.WS
CALCULAT/DPMCOMP.TMP/CHIPS/DECODER10TO7/DECODER10TO7.CST
CALCULAT/DPMCOMP.TMP/CHIPS/DECODER10TO7/DECODER10TO7.RPT
CALCULAT/DPMCOMP.TMP/CHIPS/DECODER10TO7/DECODER10TO7.WS
CALCULAT/DPMCOMP.TMP/CHIPS/DECODER10TO7_OPT/DECODER10TO7_OPT.CST
CALCULAT/DPMCOMP.TMP/CHIPS/DECODER10TO7_OPT/DECODER10TO7_OPT.RPT
CALCULAT/DPMCOMP.TMP/CHIPS/DECODER10TO7_OPT/DECODER10TO7_OPT.WS
CALCULAT/DPMCOMP.TMP/CHIPS/FREQDIVIDE/FREQDIVIDE.CST
CALCULAT/DPMCOMP.TMP/CHIPS/FREQDIVIDE/FREQDIVIDE.RPT
CALCULAT/DPMCOMP.TMP/CHIPS/FREQDIVIDE/FREQDIVIDE.WS
CALCULAT/DPMCOMP.TMP/CHIPS/FREQDIVIDE_OPT/FREQDIVIDE_OPT.CST
CALCULAT/DPMCOMP.TMP/CHIPS/FREQDIVIDE_OPT/FREQDIVIDE_OPT.RPT
CALCULAT/DPMCOMP.TMP/CHIPS/FREQDIVIDE_OPT/FREQDIVIDE_OPT.WS
CALCULAT/DPMCOMP.TMP/CHIPS/MERGE/MERGE.CST
CALCULAT/DPMCOMP.TMP/CHIPS/MERGE/MERGE.RPT
CALCULAT/DPMCOMP.TMP/CHIPS/MERGE/MERGE.WS
CALCULAT/DPMCOMP.TMP/CHIPS/MERGE_OPT/MERGE_OPT.CST
CALCULAT/DPMCOMP.TMP/CHIPS/MERGE_OPT/MERGE_OPT.RPT
CALCULAT/DPMCOMP.TMP/CHIPS/MERGE_OPT/MERGE_OPT.WS
CALCULAT/DPMCOMP.TMP/CHIPS/SCAN/SCAN.CST
CALCULAT/DPMCOMP.TMP/CHIPS/SCAN/SCAN.RPT
CALCULAT/DPMCOMP.TMP/CHIPS/SCAN/SCAN.WS
CALCULAT/DPMCOMP.TMP/CHIPS/SCAN_OPT/SCAN_OPT.CST
CALCULAT/DPMCOMP.TMP/CHIPS/SCAN_OPT/SCAN_OPT.RPT
CALCULAT/DPMCOMP.TMP/CHIPS/SCAN_OPT/SCAN_OPT.WS
CALCULAT/DPMCOMP.TMP/CHIPS/SELECTOR/SELECTOR.CST
CALCULAT/DPMCOMP.TMP/CHIPS/SELECTOR/SELECTOR.RPT
CALCULAT/DPMCOMP.TMP/CHIPS/SELECTOR/SELECTOR.WS
CALCULAT/DPMCOMP.TMP/CHIPS/SELECTOR_OPT/SELECTOR_OPT.CST
CALCULAT/DPMCOMP.TMP/CHIPS/SELECTOR_OPT/SELECTOR_OPT.RPT
CALCULAT/DPMCOMP.TMP/CHIPS/SELECTOR_OPT/SELECTOR_OPT.WS
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/ADDER%VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/ADDER%VERILOG__VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/ADDER.HNL
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/ADDER.MRA
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/ADDER.OUT
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/ADDER.STS
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/ANAL.INFO
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/ANAL.OUT
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/DECODER10TO7%VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/DECODER10TO7%VERILOG__VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/DECODER10TO7.HNL
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/DECODER10TO7.MRA
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/DECODER10TO7.OUT
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/DECODER10TO7.STS
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE%VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE%VERILOG__VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE.HNL
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE.MRA
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE.OUT
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE.STS
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE10%VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE10%VERILOG__VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE10.HNL
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE10.MRA
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE10.OUT
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE10.STS
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE2%VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE2%VERILOG__VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE2.HNL
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE2.MRA
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE2.OUT
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE2.STS
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE5%VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE5%VERILOG__VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/FREQDIVIDE5.MRA
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/MERGE%VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/MERGE%VERILOG__VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/MERGE.HNL
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/MERGE.MRA
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/MERGE.OUT
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/MERGE.STS
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/SCAN%VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/SCAN%VERILOG__VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/SCAN.HNL
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/SCAN.MRA
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/SCAN.OUT
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/SCAN.STS
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/SELECTOR%VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/SELECTOR%VERILOG__VERILOG.SYN
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/SELECTOR.HNL
CALCULAT/DPMCOMP.TMP/WORKDIRS/WORK/SELE

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