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文件名称:mem_ctrl

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    387.84kb
  • 已下载：
    0次
  • 提 供 者：
    lish****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

老外写的通用的存储器控制核，支持SDRAM SSRAM FLASH,ROM等等 8个片选信号 支持RMW cycles最大可达9*64M Bytes的存储器容量-Written by foreigners universal memory controller core, support for SDRAM SSRAM FLASH, ROM, etc. 8 chip select signals support RMW cycles up to 9* 64M Bytes of memory capacity
相关搜索： VERILOGSSRAM

(系统自动生成,下载前可以参看下载内容)

下载文件列表

mem_ctrl/bench/CVS/Entries
mem_ctrl/bench/CVS/Repository
mem_ctrl/bench/CVS/Root
mem_ctrl/bench/CVS
mem_ctrl/bench/richard/CVS/Entries
mem_ctrl/bench/richard/CVS/Repository
mem_ctrl/bench/richard/CVS/Root
mem_ctrl/bench/richard/CVS
mem_ctrl/bench/richard/verilog/bench.v
mem_ctrl/bench/richard/verilog/checkers.v
mem_ctrl/bench/richard/verilog/CVS/Entries
mem_ctrl/bench/richard/verilog/CVS/Repository
mem_ctrl/bench/richard/verilog/CVS/Root
mem_ctrl/bench/richard/verilog/CVS
mem_ctrl/bench/richard/verilog/mc_defines.v
mem_ctrl/bench/richard/verilog/models/CVS/Entries
mem_ctrl/bench/richard/verilog/models/CVS/Repository
mem_ctrl/bench/richard/verilog/models/CVS/Root
mem_ctrl/bench/richard/verilog/models/CVS
mem_ctrl/bench/richard/verilog/models/m8kx8.v
mem_ctrl/bench/richard/verilog/models/mt48lc16m16a2.v
mem_ctrl/bench/richard/verilog/models/mt58l1my18d.v
mem_ctrl/bench/richard/verilog/models
mem_ctrl/bench/richard/verilog/timescale.v
mem_ctrl/bench/richard/verilog/tst_asram.v
mem_ctrl/bench/richard/verilog/tst_multi_mem.v
mem_ctrl/bench/richard/verilog/tst_sdram.v
mem_ctrl/bench/richard/verilog/tst_ssram.v
mem_ctrl/bench/richard/verilog/wb_master_model.v
mem_ctrl/bench/richard/verilog
mem_ctrl/bench/richard
mem_ctrl/bench/verilog/160b3ver/adv_bb.v
mem_ctrl/bench/verilog/160b3ver/CVS/Entries
mem_ctrl/bench/verilog/160b3ver/CVS/Repository
mem_ctrl/bench/verilog/160b3ver/CVS/Root
mem_ctrl/bench/verilog/160b3ver/CVS
mem_ctrl/bench/verilog/160b3ver/dp160b3b.v
mem_ctrl/bench/verilog/160b3ver/DP160B3B_RU.V
mem_ctrl/bench/verilog/160b3ver/dp160b3t.v
mem_ctrl/bench/verilog/160b3ver/f160b3b.bkb
mem_ctrl/bench/verilog/160b3ver/f160b3b.bke
mem_ctrl/bench/verilog/160b3ver/f160b3b.bkt
mem_ctrl/bench/verilog/160b3ver/f160b3t.bkb
mem_ctrl/bench/verilog/160b3ver/f160b3t.bke
mem_ctrl/bench/verilog/160b3ver/f160b3t.bkt
mem_ctrl/bench/verilog/160b3ver/read.me
mem_ctrl/bench/verilog/160b3ver/t160b3b.v
mem_ctrl/bench/verilog/160b3ver/t160b3t.v
mem_ctrl/bench/verilog/160b3ver
mem_ctrl/bench/verilog/CVS/Entries
mem_ctrl/bench/verilog/CVS/Repository
mem_ctrl/bench/verilog/CVS/Root
mem_ctrl/bench/verilog/CVS
mem_ctrl/bench/verilog/sdram_models/16Mx16/CVS/Entries
mem_ctrl/bench/verilog/sdram_models/16Mx16/CVS/Repository
mem_ctrl/bench/verilog/sdram_models/16Mx16/CVS/Root
mem_ctrl/bench/verilog/sdram_models/16Mx16/CVS
mem_ctrl/bench/verilog/sdram_models/16Mx16/mt48lc16m16a2.v
mem_ctrl/bench/verilog/sdram_models/16Mx16
mem_ctrl/bench/verilog/sdram_models/16Mx8/CVS/Entries
mem_ctrl/bench/verilog/sdram_models/16Mx8/CVS/Repository
mem_ctrl/bench/verilog/sdram_models/16Mx8/CVS/Root
mem_ctrl/bench/verilog/sdram_models/16Mx8/CVS
mem_ctrl/bench/verilog/sdram_models/16Mx8/mt48lc16m8a2.v
mem_ctrl/bench/verilog/sdram_models/16Mx8
mem_ctrl/bench/verilog/sdram_models/2Mx32/bank0.txt
mem_ctrl/bench/verilog/sdram_models/2Mx32/bank1.txt
mem_ctrl/bench/verilog/sdram_models/2Mx32/bank2.txt
mem_ctrl/bench/verilog/sdram_models/2Mx32/bank3.txt
mem_ctrl/bench/verilog/sdram_models/2Mx32/CVS/Entries
mem_ctrl/bench/verilog/sdram_models/2Mx32/CVS/Repository
mem_ctrl/bench/verilog/sdram_models/2Mx32/CVS/Root
mem_ctrl/bench/verilog/sdram_models/2Mx32/CVS
mem_ctrl/bench/verilog/sdram_models/2Mx32/mt48lc2m32b2.v
mem_ctrl/bench/verilog/sdram_models/2Mx32
mem_ctrl/bench/verilog/sdram_models/32Mx8/CVS/Entries
mem_ctrl/bench/verilog/sdram_models/32Mx8/CVS/Repository
mem_ctrl/bench/verilog/sdram_models/32Mx8/CVS/Root
mem_ctrl/bench/verilog/sdram_models/32Mx8/CVS
mem_ctrl/bench/verilog/sdram_models/32Mx8/mt48lc32m8a2.v
mem_ctrl/bench/verilog/sdram_models/32Mx8
mem_ctrl/bench/verilog/sdram_models/4Mx16/bank0.txt
mem_ctrl/bench/verilog/sdram_models/4Mx16/bank1.txt
mem_ctrl/bench/verilog/sdram_models/4Mx16/bank2.txt
mem_ctrl/bench/verilog/sdram_models/4Mx16/bank3.txt
mem_ctrl/bench/verilog/sdram_models/4Mx16/CVS/Entries
mem_ctrl/bench/verilog/sdram_models/4Mx16/CVS/Repository
mem_ctrl/bench/verilog/sdram_models/4Mx16/CVS/Root
mem_ctrl/bench/verilog/sdram_models/4Mx16/CVS
mem_ctrl/bench/verilog/sdram_models/4Mx16/mt48lc4m16a2.v
mem_ctrl/bench/verilog/sdram_models/4Mx16
mem_ctrl/bench/verilog/sdram_models/4Mx32/CVS/Entries
mem_ctrl/bench/verilog/sdram_models/4Mx32/CVS/Repository
mem_ctrl/bench/verilog/sdram_models/4Mx32/CVS/Root
mem_ctrl/bench/verilog/sdram_models/4Mx32/CVS
mem_ctrl/bench/verilog/sdram_models/4Mx32/mt48lc4m32b2.v
mem_ctrl/bench/verilog/sdram_models/4Mx32
mem_ctrl/bench/verilog/sdram_models/8Mx16/CVS/Entries
mem_ctrl/bench/verilog/sdram_models/8Mx16/CVS/Repository
mem_ctrl/bench/verilog/sdram_models/8Mx16/CVS/Root
mem_ctrl/bench/verilog/sdram_models/8Mx16/CVS
mem_ctrl/bench/verilog/sdram_models/8Mx16/mt48lc8m16a2.v
mem_ctrl/bench/verilog/sdram_models/8Mx16
mem_ctrl/bench/verilog/sdram_models/8Mx8/bank0.txt
mem_ctrl/bench/verilog/sdram_models/8Mx8/bank1.txt
mem_ctrl/bench/verilog/sdram_models/8Mx8/bank2.txt
mem_ctrl/bench/verilog/sdram_models/8Mx8/bank3.txt
mem_ctrl/bench/verilog/sdram_models/8Mx8/CVS/Entries
mem_ctrl/bench/verilog/sdram_models/8Mx8/CVS/Repository
mem_ctrl/bench/verilog/sdram_models/8Mx8/CVS/Root
mem_ctrl/bench/verilog/sdram_models/8Mx8/CVS
mem_ctrl/bench/verilog

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