文件名称:fpgacis
-
所属分类:
- 标签属性:
- 上传时间:2012-11-16
-
文件大小:1.05mb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
主要是通过使用FPGA利用CIS(接触式图像传感器)进行图像采集,通过AD转换之后把数据存储到FPGA里面开辟的FIFO-Mainly through the use of FPGA utilization of CIS (non-contact image sensor) image acquisition, through the data storage after AD transform to open the FIFO FPGA inside
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FPGA_cis control/AD.lfp
FPGA_cis control/AD.ucf
FPGA_cis control/ADControl.ise
FPGA_cis control/ADControl.ise_ISE_Backup
FPGA_cis control/ADControl.mcs
FPGA_cis control/ADControl.prm
FPGA_cis control/ADControl.sig
FPGA_cis control/automake.log
FPGA_cis control/bbs_lock
FPGA_cis control/core.tpl
FPGA_cis control/ADControl.dhp
FPGA_cis control/dcm1_arwz.xaw
FPGA_cis control/dcm1_arwz_arwz.ucf
FPGA_cis control/dcm2_arwz.xaw
FPGA_cis control/dcm2_arwz_arwz.ucf
FPGA_cis control/dcm3_arwz.xaw
FPGA_cis control/dcm3_arwz_arwz.ucf
FPGA_cis control/dds_ip.asy
FPGA_cis control/dds_ip.edn
FPGA_cis control/dds_ip.ngo
FPGA_cis control/dds_ip.sym
FPGA_cis control/dds_ip.v
FPGA_cis control/dds_ip.veo
FPGA_cis control/dds_ip.vhd
FPGA_cis control/dds_ip.vho
FPGA_cis control/dds_ip.xco
FPGA_cis control/dds_ip_flist.txt
FPGA_cis control/dds_ip_readme.txt
FPGA_cis control/dds_ip_SINCOS_TABLE_TRIG_ROM.mif
FPGA_cis control/fifo_ip.asy
FPGA_cis control/fifo_ip.edn
FPGA_cis control/fifo_ip.ngo
FPGA_cis control/fifo_ip.sym
FPGA_cis control/fifo_ip.v
FPGA_cis control/fifo_ip.veo
FPGA_cis control/fifo_ip.vhd
FPGA_cis control/fifo_ip.vho
FPGA_cis control/fifo_ip.xco
FPGA_cis control/fifo_ip_fifo_generator_v2_0_as_1.ngc
FPGA_cis control/fifo_ip_fifo_generator_v2_0_ss_1.ngc
FPGA_cis control/fifo_ip_flist.txt
FPGA_cis control/fifo_ip_readme.txt
FPGA_cis control/Flash_Array.ucf
FPGA_cis control/FPGA_USB_JP2.ucf
FPGA_cis control/main_summary.html
FPGA_cis control/FPGA_USB_JP5.lfp
FPGA_cis control/FPGA_USB_JP5.ucf
FPGA_cis control/main.lfp
FPGA_cis control/ts2.tbw
FPGA_cis control/ts2.udo
FPGA_cis control/ts2.xwv
FPGA_cis control/main.vhd
FPGA_cis control/main_cclktemp.bit
FPGA_cis control/tws.xwv
FPGA_cis control/pepExtractor.prj
FPGA_cis control/prjname.lso
FPGA_cis control/userlang.tpl
FPGA_cis control/_cg_exc.out
FPGA_cis control/_pace.ucf
FPGA_cis control/__projnav.log
FPGA_cis control/test.ucf
FPGA_cis control/test.lfp
FPGA_cis control/tws.xwv_bak
FPGA_cis control/ADControl.ipf
FPGA_cis control/tws.tbw
FPGA_cis control/tws.udo
FPGA_cis control/transcript
FPGA_cis control/results.txt
FPGA_cis control/tws.jhd
FPGA_cis control/tws.vhw
FPGA_cis control/ts2.xwv_bak
FPGA_cis control/tws.ant
FPGA_cis control/work/_info
FPGA_cis control/work/ts2/testbench_arch.asm
FPGA_cis control/work/ts2/testbench_arch.dat
FPGA_cis control/work/ts2/_primary.dat
FPGA_cis control/work/tws/_primary.dat
FPGA_cis control/work/tws/testbench_arch.dat
FPGA_cis control/work/tws/testbench_arch.asm
FPGA_cis control/work/main/_primary.dat
FPGA_cis control/work/main/behavioral.dat
FPGA_cis control/work/main/behavioral.asm
FPGA_cis control/work/main/structure.dat
FPGA_cis control/work/main/structure.asm
FPGA_cis control/work/dds_ip/_primary.dat
FPGA_cis control/work/dds_ip/xilinx.dat
FPGA_cis control/work/dds_ip/xilinx.asm
FPGA_cis control/work/fifo_ip/_primary.dat
FPGA_cis control/work/fifo_ip/fifo_ip_a.dat
FPGA_cis control/work/fifo_ip/fifo_ip_a.asm
FPGA_cis control/__projnav/parentAssignPackagePinsApp_tcl.rsp
FPGA_cis control/__projnav/parentCreateAreaConstraintsApp_tcl.rsp
FPGA_cis control/__projnav/runXst_tcl.rsp
FPGA_cis control/__projnav/sumrpt_tcl.rsp
FPGA_cis control/__projnav/xst_sprjTOstx_tcl.rsp
FPGA_cis control/__projnav/netgen_par_tcl.rsp
FPGA_cis control/__projnav/ADControl.gfl
FPGA_cis control/_ngo/dds_ip.ngo
FPGA_cis control/_ngo/fifo_ip.ngo
FPGA_cis control/_ngo/netlist.lst
FPGA_cis control/_cg/_cg_exc.out
FPGA_cis control/work/ts2
FPGA_cis control/work/tws
FPGA_cis control/work/main
FPGA_cis control/work/dds_ip
FPGA_cis control/work/fifo_ip
FPGA_cis control/ADControl_xdb/tmp
FPGA_cis control/work
FPGA_cis control/__projnav
FPGA_cis control/_xmsgs
FPGA_cis control/_ngo
FPGA_cis control/_cg
FPGA_cis control/ADControl_xdb
FPGA_cis control
FPGA_cis control/AD.ucf
FPGA_cis control/ADControl.ise
FPGA_cis control/ADControl.ise_ISE_Backup
FPGA_cis control/ADControl.mcs
FPGA_cis control/ADControl.prm
FPGA_cis control/ADControl.sig
FPGA_cis control/automake.log
FPGA_cis control/bbs_lock
FPGA_cis control/core.tpl
FPGA_cis control/ADControl.dhp
FPGA_cis control/dcm1_arwz.xaw
FPGA_cis control/dcm1_arwz_arwz.ucf
FPGA_cis control/dcm2_arwz.xaw
FPGA_cis control/dcm2_arwz_arwz.ucf
FPGA_cis control/dcm3_arwz.xaw
FPGA_cis control/dcm3_arwz_arwz.ucf
FPGA_cis control/dds_ip.asy
FPGA_cis control/dds_ip.edn
FPGA_cis control/dds_ip.ngo
FPGA_cis control/dds_ip.sym
FPGA_cis control/dds_ip.v
FPGA_cis control/dds_ip.veo
FPGA_cis control/dds_ip.vhd
FPGA_cis control/dds_ip.vho
FPGA_cis control/dds_ip.xco
FPGA_cis control/dds_ip_flist.txt
FPGA_cis control/dds_ip_readme.txt
FPGA_cis control/dds_ip_SINCOS_TABLE_TRIG_ROM.mif
FPGA_cis control/fifo_ip.asy
FPGA_cis control/fifo_ip.edn
FPGA_cis control/fifo_ip.ngo
FPGA_cis control/fifo_ip.sym
FPGA_cis control/fifo_ip.v
FPGA_cis control/fifo_ip.veo
FPGA_cis control/fifo_ip.vhd
FPGA_cis control/fifo_ip.vho
FPGA_cis control/fifo_ip.xco
FPGA_cis control/fifo_ip_fifo_generator_v2_0_as_1.ngc
FPGA_cis control/fifo_ip_fifo_generator_v2_0_ss_1.ngc
FPGA_cis control/fifo_ip_flist.txt
FPGA_cis control/fifo_ip_readme.txt
FPGA_cis control/Flash_Array.ucf
FPGA_cis control/FPGA_USB_JP2.ucf
FPGA_cis control/main_summary.html
FPGA_cis control/FPGA_USB_JP5.lfp
FPGA_cis control/FPGA_USB_JP5.ucf
FPGA_cis control/main.lfp
FPGA_cis control/ts2.tbw
FPGA_cis control/ts2.udo
FPGA_cis control/ts2.xwv
FPGA_cis control/main.vhd
FPGA_cis control/main_cclktemp.bit
FPGA_cis control/tws.xwv
FPGA_cis control/pepExtractor.prj
FPGA_cis control/prjname.lso
FPGA_cis control/userlang.tpl
FPGA_cis control/_cg_exc.out
FPGA_cis control/_pace.ucf
FPGA_cis control/__projnav.log
FPGA_cis control/test.ucf
FPGA_cis control/test.lfp
FPGA_cis control/tws.xwv_bak
FPGA_cis control/ADControl.ipf
FPGA_cis control/tws.tbw
FPGA_cis control/tws.udo
FPGA_cis control/transcript
FPGA_cis control/results.txt
FPGA_cis control/tws.jhd
FPGA_cis control/tws.vhw
FPGA_cis control/ts2.xwv_bak
FPGA_cis control/tws.ant
FPGA_cis control/work/_info
FPGA_cis control/work/ts2/testbench_arch.asm
FPGA_cis control/work/ts2/testbench_arch.dat
FPGA_cis control/work/ts2/_primary.dat
FPGA_cis control/work/tws/_primary.dat
FPGA_cis control/work/tws/testbench_arch.dat
FPGA_cis control/work/tws/testbench_arch.asm
FPGA_cis control/work/main/_primary.dat
FPGA_cis control/work/main/behavioral.dat
FPGA_cis control/work/main/behavioral.asm
FPGA_cis control/work/main/structure.dat
FPGA_cis control/work/main/structure.asm
FPGA_cis control/work/dds_ip/_primary.dat
FPGA_cis control/work/dds_ip/xilinx.dat
FPGA_cis control/work/dds_ip/xilinx.asm
FPGA_cis control/work/fifo_ip/_primary.dat
FPGA_cis control/work/fifo_ip/fifo_ip_a.dat
FPGA_cis control/work/fifo_ip/fifo_ip_a.asm
FPGA_cis control/__projnav/parentAssignPackagePinsApp_tcl.rsp
FPGA_cis control/__projnav/parentCreateAreaConstraintsApp_tcl.rsp
FPGA_cis control/__projnav/runXst_tcl.rsp
FPGA_cis control/__projnav/sumrpt_tcl.rsp
FPGA_cis control/__projnav/xst_sprjTOstx_tcl.rsp
FPGA_cis control/__projnav/netgen_par_tcl.rsp
FPGA_cis control/__projnav/ADControl.gfl
FPGA_cis control/_ngo/dds_ip.ngo
FPGA_cis control/_ngo/fifo_ip.ngo
FPGA_cis control/_ngo/netlist.lst
FPGA_cis control/_cg/_cg_exc.out
FPGA_cis control/work/ts2
FPGA_cis control/work/tws
FPGA_cis control/work/main
FPGA_cis control/work/dds_ip
FPGA_cis control/work/fifo_ip
FPGA_cis control/ADControl_xdb/tmp
FPGA_cis control/work
FPGA_cis control/__projnav
FPGA_cis control/_xmsgs
FPGA_cis control/_ngo
FPGA_cis control/_cg
FPGA_cis control/ADControl_xdb
FPGA_cis control
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.