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文件名称:FPGApro

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    2008-10-13
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    1.17mb
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VERILOG HDL 实际工控项目源码

开发工具 altera quartus2-verilog HDL actual industrial projects source development tools altera quartus2
(系统自动生成,下载前可以参看下载内容)

下载文件列表

FPGApro/myfifo.qpf
FPGApro/myfifo.qsf
FPGApro/myram.v
FPGApro/myram.bsf
FPGApro/myram_bb.v
FPGApro/myfifo.bdf
FPGApro/myfifo.map.rpt
FPGApro/myfifo.flow.rpt
FPGApro/myfifo.map.summary
FPGApro/myfifo.map.eqn
FPGApro/myfifo.fit.eqn
FPGApro/myfifo.pin
FPGApro/myfifo.fit.rpt
FPGApro/myfifo.fit.summary
FPGApro/myfifo.sof
FPGApro/myfifo.pof
FPGApro/myfifo.asm.rpt
FPGApro/myfifo.tan.summary
FPGApro/myfifo.tan.rpt
FPGApro/myfifo.eda.rpt
FPGApro/myfifo.done
FPGApro/myfifo.qws
FPGApro/cmp_state.ini
FPGApro/sim.cfg
FPGApro/wram.bsf
FPGApro/wram.v
FPGApro/myfifo_assignment_defaults.qdf
FPGApro/addr_code.bdf
FPGApro/myfifo.fld
FPGApro/myfifo.cdf
FPGApro/myfifo_epc.svf
FPGApro/myfifo_epc.jam
FPGApro/myfifo.jam
FPGApro/serv_req_info.txt
FPGApro/watchdog.v
FPGApro/ram.v
FPGApro/addr_code.v
FPGApro/ram_all.bdf
FPGApro/add_decode.v
FPGApro/ram_all.v
FPGApro/myfifo.sim.rpt
FPGApro/sopc_builder_debug_log.txt
FPGApro/pan.ptf
FPGApro/pan.v
FPGApro/pan.ptf.bak
FPGApro/myfifo.jbc
FPGApro/myfifo.ttf
FPGApro/myfifo.rbf
FPGApro/myfifo.hexout
FPGApro/myfifo.vwf
FPGApro/ad_collect.v
FPGApro/mydram.v.bak
FPGApro/ram.v.bak
FPGApro/mydram.v
FPGApro/db/myfifo.syn_hier_info
FPGApro/db/myfifo.fit.qmsg
FPGApro/db/myfifo.map.qmsg
FPGApro/db/myfifo.(0).cnf.cdb
FPGApro/db/myfifo.asm.qmsg
FPGApro/db/myfifo.tan.qmsg
FPGApro/db/myfifo.(0).cnf.hdb
FPGApro/db/mux_jpd.tdf
FPGApro/db/myfifo.(1).cnf.cdb
FPGApro/db/myfifo.eda.qmsg
FPGApro/db/myfifo.(1).cnf.hdb
FPGApro/db/myfifo_cmp.qrpt
FPGApro/db/myfifo.(35).cnf.cdb
FPGApro/db/myfifo.(2).cnf.cdb
FPGApro/db/myfifo.(2).cnf.hdb
FPGApro/db/myfifo.(3).cnf.cdb
FPGApro/db/myfifo.(3).cnf.hdb
FPGApro/db/myfifo.rtlv_sg_swap.cdb
FPGApro/db/myfifo.rpp.qmsg
FPGApro/db/myfifo.(5).cnf.cdb
FPGApro/db/myfifo.(5).cnf.hdb
FPGApro/db/myfifo.(6).cnf.cdb
FPGApro/db/myfifo.(6).cnf.hdb
FPGApro/db/myfifo.(7).cnf.cdb
FPGApro/db/myfifo.(7).cnf.hdb
FPGApro/db/myfifo.cmp.rdb
FPGApro/db/myfifo.(4).cnf.cdb
FPGApro/db/myfifo.hier_info
FPGApro/db/myfifo.(31).cnf.cdb
FPGApro/db/myfifo.sim.vwf
FPGApro/db/add_sub_soh.tdf
FPGApro/db/myfifo.sim.hdb
FPGApro/db/mux_kgc.tdf
FPGApro/db/myfifo.(9).cnf.cdb
FPGApro/db/myfifo.(9).cnf.hdb
FPGApro/db/decode_nkb.tdf
FPGApro/db/myfifo.(10).cnf.cdb
FPGApro/db/myfifo.(10).cnf.hdb
FPGApro/db/myfifo.(11).cnf.cdb
FPGApro/db/myfifo.(11).cnf.hdb
FPGApro/db/myfifo.(12).cnf.cdb
FPGApro/db/myfifo.(12).cnf.hdb
FPGApro/db/myfifo.(13).cnf.cdb
FPGApro/db/myfifo.(13).cnf.hdb
FPGApro/db/myfifo.(14).cnf.cdb
FPGApro/db/add_sub_fnh.tdf
FPGApro/db/myfifo.(14).cnf.hdb
FPGApro/db/myfifo.(15).cnf.cdb
FPGApro/db/myfifo.(15).cnf.hdb
FPGApro/db/myfifo.(16).cnf.cdb
FPGApro/db/myfifo.(16).cnf.hdb
FPGApro/db/myfifo.(17).cnf.cdb
FPGApro/db/myfifo.(17).cnf.hdb
FPGApro/db/myfifo.(18).cnf.cdb
FPGApro/db/add_sub_enh.tdf
FPGApro/db/myfifo.(18).cnf.hdb
FPGApro/db/myfifo.(19).cnf.cdb
FPGApro/db/myfifo.(19).cnf.hdb
FPGApro/db/add_sub_qjh.tdf
FPGApro/db/myfifo.(20).cnf.cdb
FPGApro/db/myfifo.(20).cnf.hdb
FPGApro/db/myfifo.(21).cnf.cdb
FPGApro/db/myfifo.(21).cnf.hdb
FPGApro/db/myfifo.(22).cnf.cdb
FPGApro/db/myfifo.(22).cnf.hdb
FPGApro/db/myfifo.(23).cnf.cdb
FPGApro/db/myfifo.(23).cnf.hdb
FPGApro/db/myfifo.(4).cnf.hdb
FPGApro/db/myfifo.(8).cnf.cdb
FPGApro/db/myfifo.(24).cnf.cdb
FPGApro/db/myfifo.(8).cnf.hdb
FPGApro/db/myfifo.(26).cnf.cdb
FPGApro/db/myfifo.(24).cnf.hdb
FPGApro/db/myfifo.(58).cnf.cdb
FPGApro/db/myfifo.(26).cnf.hdb
FPGApro/db/myfifo.(25).cnf.cdb
FPGApro/db/myfifo.(33).cnf.cdb
FPGApro/db/myfifo.frm.hdb
FPGApro/db/myfifo.(25).cnf.hdb
FPGApro/db/myfifo.(31).cnf.hdb
FPGApro/db/myfifo.(32).cnf.cdb
FPGApro/db/myfifo.(27).cnf.cdb
FPGApro/db/myfifo.(27).cnf.hdb
FPGApro/db/myfifo.(28).cnf.cdb
FPGApro/db/myfifo.(28).cnf.hdb
FPGApro/db/myfifo.sim.qmsg
FPGApro/db/myfifo.(29).cnf.cdb
FPGApro/db/myfifo.(29).cnf.hdb
FPGApro/db/myfifo.(30).cnf.cdb
FPGApro/db/myfifo.(30).cnf.hdb
FPGApro/db/myfifo.(37).cnf.cdb
FPGApro/db/myfifo.(32).cnf.hdb
FPGApro/db/myfifo.(56).cnf.cdb
FPGApro/db/myfifo.sgate.rvd
FPGApro/db/add_sub_dnh.tdf
FPGApro/db/myfifo.swb.qmsg
FPGApro/db/myfifo.(33).cnf.hdb
FPGApro/db/add_sub_voh.tdf
FPGApro/db/myfifo.(63).cnf.cdb
FPGApro/db/myfifo.(34).cnf.cdb
FPGApro/db/myfifo.(34).cnf.hdb
FPGApro/db/add_sub_qoh.tdf
FPGApro/db/add_sub_ooh.tdf
FPGApro/db/add_sub_0ph.tdf
FPGApro/db/myfifo_sim.qrpt
FPGApro/db/myfifo.(39).cnf.cdb
FPGApro/db/myfifo.sim.rdb
FPGApro/db/myfifo.(35).cnf.hdb
FPGApro/db/myfifo.(36).cnf.cdb
FPGApro/db/myfifo.atom.rvd
FPGApro/db/mux_ddc.tdf
FPGApro/db/myfifo.fnsim.hdb
FPGApro/db/myfifo.(37).cnf.hdb
FPGApro/db/mux_tec.tdf
FPGApro/db/myfifo.(36).cnf.hdb
FPGApro/db/add_sub_poh.tdf
FPGApro/db/add_sub_uoh.tdf
FPGApro/db/myfifo.db_info
FPGApro/db/myfifo.hif
FPGApro/db/myfifo.(38).cnf.cdb
FPGApro/db/myfifo.(38).cnf.hdb
FPGApro/db/myfifo.(41).cnf.cdb
FPGApro/db/myfifo.(39).cnf.hdb
FPGApro/db/myfifo.(40).cnf.cdb
FPGApro/db/myfifo.rtlv.hdb
FPGApro/db/myfifo.(41).cnf.hdb
FPGApro/db/myfifo.(40).cnf.hdb
FPGApro/db/myfifo.(51).cnf.cdb
FPGApro/db/myfifo.(42).cnf.cdb
FPGApro/db/myfifo.(42).cnf.hdb
FPGApro/db/myfifo.(43).cnf.cdb
FPGApro/db/myfifo.(43).cnf.hdb
FPGApro/db/myfifo.(44).cnf.cdb
FPGApro/db/myfifo.(77).cnf.cdb
FPGApro/db/myfifo.(44).cnf.hdb

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