文件名称:DE2_lab_exercises
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- 上传时间:2012-11-16
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文件大小:2.07mb
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这是台湾友晶科技为DE2 FPGA开发板所提供的学习资料,非常适合大学数字电路的学习以及FPGA入门的人学习。-This is the Friends of the crystal technology DE2 FPGA development board provides learning materials, is ideal for university study and FPGA digital circuit who started learning.
相关搜索: vhdl
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下载文件列表
DE2_lab_exercises/DE2_Computer_Organization/lab1.pdf
DE2_lab_exercises/DE2_Computer_Organization/lab2.pdf
DE2_lab_exercises/DE2_Computer_Organization/lab3.pdf
DE2_lab_exercises/DE2_Computer_Organization/lab4.pdf
DE2_lab_exercises/DE2_Computer_Organization/lab5.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab10_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab1_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab2_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab3_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab4_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab5_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab6_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab7_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab8_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab9_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab10_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab1_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab2_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab3_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab4_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab5_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab6_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab7_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab8_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab9_VHDL.pdf
DE2_lab_exercises/DE2_pin_assignments.csv
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl
DE2_lab_exercises/DE2_Computer_Organization
DE2_lab_exercises/DE2_Digital_Logic
DE2_lab_exercises
DE2_lab_exercises/DE2_Computer_Organization/lab2.pdf
DE2_lab_exercises/DE2_Computer_Organization/lab3.pdf
DE2_lab_exercises/DE2_Computer_Organization/lab4.pdf
DE2_lab_exercises/DE2_Computer_Organization/lab5.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab10_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab1_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab2_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab3_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab4_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab5_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab6_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab7_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab8_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog/lab9_Verilog.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab10_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab1_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab2_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab3_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab4_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab5_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab6_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab7_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab8_VHDL.pdf
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl/lab9_VHDL.pdf
DE2_lab_exercises/DE2_pin_assignments.csv
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_verilog
DE2_lab_exercises/DE2_Digital_Logic/DE2_labs_vhdl
DE2_lab_exercises/DE2_Computer_Organization
DE2_lab_exercises/DE2_Digital_Logic
DE2_lab_exercises
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