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文件名称:Two_port_RAMa

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    215.33kb
  • 已下载：
    0次
  • 提 供 者：
    蓝***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

Mactel公司的TWO PORT RAM的详细使用指南，通过具体的实例，解释的特别清楚，对于使用actel公司的fpga芯片来说帮助很大！-TWO PORT RAM Mactel' s detailed user guide, through specific examples to explain the particularly clear, for use actel fpga chip company is very helpful!
相关搜索： ram actel

(系统自动生成,下载前可以参看下载内容)

下载文件列表

Two_port_RAM/smartgen/two_portRAM/two_portRAM.gen
Two_port_RAM/smartgen/two_portRAM/two_portRAM.log
Two_port_RAM/smartgen/two_portRAM/two_portRAM.shx
Two_port_RAM/smartgen/two_portRAM/two_portRAM_R0C0.mem
Two_port_RAM/smartgen/two_portRAM/two_portRAM.cxf
Two_port_RAM/smartgen/two_portRAM/two_portRAM.v
Two_port_RAM/smartgen/two_portRAM_work.ixf
Two_port_RAM/smartgen/smartgen.aws
Two_port_RAM/hdl/Wr_Re_ctrl.v
Two_port_RAM/hdl/top.v
Two_port_RAM/hdl/hdlsynchk.tcl
Two_port_RAM/viewdraw/vf/project.lst
Two_port_RAM/viewdraw/viewdraw.ini
Two_port_RAM/simulation/run.do
Two_port_RAM/simulation/modelsim.log
Two_port_RAM/simulation/postsynth/_info
Two_port_RAM/simulation/postsynth/read_wirte_ram/_primary.vhd
Two_port_RAM/simulation/postsynth/read_wirte_ram/verilog.psm
Two_port_RAM/simulation/postsynth/read_wirte_ram/_primary.dat
Two_port_RAM/simulation/postsynth/two_port@r@a@m/_primary.vhd
Two_port_RAM/simulation/postsynth/two_port@r@a@m/verilog.psm
Two_port_RAM/simulation/postsynth/two_port@r@a@m/_primary.dat
Two_port_RAM/simulation/postsynth/top/_primary.vhd
Two_port_RAM/simulation/postsynth/top/verilog.psm
Two_port_RAM/simulation/postsynth/top/_primary.dat
Two_port_RAM/simulation/postsynth/stimulus/_primary.vhd
Two_port_RAM/simulation/postsynth/stimulus/verilog.psm
Two_port_RAM/simulation/postsynth/stimulus/_primary.dat
Two_port_RAM/simulation/postsynth/tb_clock_minmax/_primary.vhd
Two_port_RAM/simulation/postsynth/tb_clock_minmax/verilog.psm
Two_port_RAM/simulation/postsynth/tb_clock_minmax/_primary.dat
Two_port_RAM/simulation/postsynth/testbench/_primary.vhd
Two_port_RAM/simulation/postsynth/testbench/verilog.psm
Two_port_RAM/simulation/postsynth/testbench/_primary.dat
Two_port_RAM/simulation/vsim.wlf
Two_port_RAM/simulation/presynth/_info
Two_port_RAM/simulation/presynth/two_port@r@a@m/_primary.vhd
Two_port_RAM/simulation/presynth/two_port@r@a@m/verilog.psm
Two_port_RAM/simulation/presynth/two_port@r@a@m/_primary.dat
Two_port_RAM/simulation/presynth/read_wirte_ram/_primary.vhd
Two_port_RAM/simulation/presynth/read_wirte_ram/verilog.psm
Two_port_RAM/simulation/presynth/read_wirte_ram/_primary.dat
Two_port_RAM/simulation/presynth/top/_primary.vhd
Two_port_RAM/simulation/presynth/top/verilog.psm
Two_port_RAM/simulation/presynth/top/_primary.dat
Two_port_RAM/simulation/presynth/stimulus/_primary.vhd
Two_port_RAM/simulation/presynth/stimulus/verilog.psm
Two_port_RAM/simulation/presynth/stimulus/_primary.dat
Two_port_RAM/simulation/presynth/tb_clock_minmax/_primary.vhd
Two_port_RAM/simulation/presynth/tb_clock_minmax/verilog.psm
Two_port_RAM/simulation/presynth/tb_clock_minmax/_primary.dat
Two_port_RAM/simulation/presynth/testbench/_primary.vhd
Two_port_RAM/simulation/presynth/testbench/verilog.psm
Two_port_RAM/simulation/presynth/testbench/_primary.dat
Two_port_RAM/simulation/modelsim.ini.sav
Two_port_RAM/simulation/meminit.dat
Two_port_RAM/simulation/two_portRAM_R0C0.mem
Two_port_RAM/simulation/modelsim.ini
Two_port_RAM/synthesis/stdout.log
Two_port_RAM/synthesis/syntmp/top_flink.htm
Two_port_RAM/synthesis/syntmp/top_srr.htm
Two_port_RAM/synthesis/syntmp/top_toc.htm
Two_port_RAM/synthesis/syntmp/sap.log
Two_port_RAM/synthesis/syntmp/top.plg
Two_port_RAM/synthesis/syntmp/top.msg
Two_port_RAM/synthesis/top.srr
Two_port_RAM/synthesis/top.htm
Two_port_RAM/synthesis/top.tlg
Two_port_RAM/synthesis/top.fse
Two_port_RAM/synthesis/traplog.tlg
Two_port_RAM/synthesis/.recordref
Two_port_RAM/synthesis/top.srd
Two_port_RAM/synthesis/top.srm
Two_port_RAM/synthesis/top.map
Two_port_RAM/synthesis/top.edn
Two_port_RAM/synthesis/top.sdf
Two_port_RAM/synthesis/top_sdc.sdc
Two_port_RAM/synthesis/top.areasrr
Two_port_RAM/synthesis/top_drc.rpt
Two_port_RAM/synthesis/top_syn.prd
Two_port_RAM/synthesis/top.v
Two_port_RAM/synthesis/top.srs
Two_port_RAM/synthesis/top.sap
Two_port_RAM/synthesis/top_syn.prj
Two_port_RAM/stimulus/top.hpj
Two_port_RAM/stimulus/waveperl.log
Two_port_RAM/stimulus/BtimErrors.log
Two_port_RAM/stimulus/files_to_build.txt
Two_port_RAM/stimulus/top_tbench.btim
Two_port_RAM/stimulus/top.dsk
Two_port_RAM/stimulus/top_tbench.v
Two_port_RAM/stimulus/top_tbench.bk
Two_port_RAM/designer/impl1/top.tcl
Two_port_RAM/designer/impl1/designer_genhdl.log
Two_port_RAM/Two_port_RAM.prj
Two_port_RAM/simulation/postsynth/_temp
Two_port_RAM/simulation/postsynth/read_wirte_ram
Two_port_RAM/simulation/postsynth/two_port@r@a@m
Two_port_RAM/simulation/postsynth/top
Two_port_RAM/simulation/postsynth/stimulus
Two_port_RAM/simulation/postsynth/tb_clock_minmax
Two_port_RAM/simulation/postsynth/testbench
Two_port_RAM/simulation/presynth/_temp
Two_port_RAM/simulation/presynth/two_port@r@a@m
Two_port_RAM/simulation/presynth/read_wirte_ram
Two_port_RAM/simulation/presynth/top
Two_port_RAM/simulation/presynth/stimulus
Two_port_RAM/simulation/presynth/tb_clock_minmax
Two_port_RAM/simulation/presynth/testbench
Two_port_RAM/designer/impl1/simulation
Two_port_RAM/smartgen/two_portRAM
Two_port_RAM/viewdraw/vf
Two_port_RAM/viewdraw/sch
Two_port_RAM/viewdraw/sym
Two_port_RAM/viewdraw/wir
Two_port_RAM/simulation/postsynth
Two_port_RAM/simulation/presynth
Two_port_RAM/synthes

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