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文件名称:ISE_final10.1

  • 所属分类：
    Other Embeded program
  • 标签属性：
    [Matlab] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    19.94mb
  • 已下载：
    0次
  • 提 供 者：
    刘****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

这是一个xinlinx公司在09年北京市电子竞赛的几个实例，拥有一定的代表性，是学习嵌入式开发的好帮手。-This is a xinlinx Beijing in 2009 a few examples of e-competition, with some representation of embedded development is to learn a good helper.
相关搜索： 电子 竞赛

(系统自动生成,下载前可以参看下载内容)

下载文件列表

KCPSM3
KCPSM3/Assembler
KCPSM3/Assembler/int_test.psm
KCPSM3/Assembler/KCPSM3.EXE
KCPSM3/Assembler/ROM_form.coe
KCPSM3/Assembler/ROM_form.v
KCPSM3/Assembler/ROM_form.vhd
KCPSM3/Assembler/uclock.psm
KCPSM3/Docs
KCPSM3/Docs/KCPSM3_Manual.pdf
KCPSM3/Docs/UART_Manual.pdf
KCPSM3/Docs/UART_real_time_clock.pdf
KCPSM3/Docs/ug129.pdf
KCPSM3/kcpsm3.ngc
KCPSM3/read_me.txt
KCPSM3/Verilog
KCPSM3/Verilog/bbfifo_16x8.v
KCPSM3/Verilog/embedded_kcpsm3.v
KCPSM3/Verilog/kcpsm3.v
KCPSM3/Verilog/kcpsm3_int_test.v
KCPSM3/Verilog/kcuart_rx.v
KCPSM3/Verilog/kcuart_tx.v
KCPSM3/Verilog/testbench.v
KCPSM3/Verilog/uart_clock.v
KCPSM3/Verilog/uart_rx.v
KCPSM3/Verilog/uart_tx.v
KCPSM3/VHDL
KCPSM3/VHDL/bbfifo_16x8.vhd
KCPSM3/VHDL/embedded_kcpsm3.vhd
KCPSM3/VHDL/kcpsm3.vhd
KCPSM3/VHDL/kcpsm3_int_test.vhd
KCPSM3/VHDL/kcuart_rx.vhd
KCPSM3/VHDL/kcuart_tx.vhd
KCPSM3/VHDL/test_bench.vhd
KCPSM3/VHDL/uart_clock.vhd
KCPSM3/VHDL/uart_rx.vhd
KCPSM3/VHDL/uart_tx.vhd
labsolutions
labsolutions/VHDL
labsolutions/VHDL/lab1
labsolutions/VHDL/lab1/Assembler
labsolutions/VHDL/lab1/Assembler/CONSTANT.TXT
labsolutions/VHDL/lab1/Assembler/INT_TEST.COE
labsolutions/VHDL/lab1/Assembler/INT_TEST.DEC
labsolutions/VHDL/lab1/Assembler/INT_TEST.FMT
labsolutions/VHDL/lab1/Assembler/INT_TEST.HEX
labsolutions/VHDL/lab1/Assembler/INT_TEST.LOG
labsolutions/VHDL/lab1/Assembler/INT_TEST.M
labsolutions/VHDL/lab1/Assembler/int_test.psm
labsolutions/VHDL/lab1/Assembler/INT_TEST.V
labsolutions/VHDL/lab1/Assembler/INT_TEST.VHD
labsolutions/VHDL/lab1/Assembler/KCPSM3.EXE
labsolutions/VHDL/lab1/Assembler/LABELS.TXT
labsolutions/VHDL/lab1/Assembler/PASS1.DAT
labsolutions/VHDL/lab1/Assembler/PASS2.DAT
labsolutions/VHDL/lab1/Assembler/PASS3.DAT
labsolutions/VHDL/lab1/Assembler/PASS4.DAT
labsolutions/VHDL/lab1/Assembler/PASS5.DAT
labsolutions/VHDL/lab1/Assembler/ROM_form.coe
labsolutions/VHDL/lab1/Assembler/ROM_form.v
labsolutions/VHDL/lab1/Assembler/ROM_form.vhd
labsolutions/VHDL/lab1/Assembler/uclock.psm
labsolutions/VHDL/lab1/Flow_Lab
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/1.jhd
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/1.sch
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/1.schlog
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab.ise
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab.ntrc_log
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab.restore
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/cst.xbcd
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/version
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/Autonym
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/common
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/__stored_object_table__
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/ISimPlugin
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/ISimPlugin/SignalOrdering1
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/ISimPlugin/SignalOrdering1/testbench_isim_beh.exe
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/ISimPlugin/SignalOrdering1/testbench_isim_beh.exe_StrTbl
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/PnAutoRun
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/NameMap
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/NameMap_StrTbl
labsolutions/VHDL/lab1/Flow_Lab/Flow_Lab/Flow_Lab_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/__stored_objects__
labsolutions/VHDL/

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