使用VHDL进行分频器设计

本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设

计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数

（N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可

通过Synplify Pro或FPGA生产厂商的综合器进行综合，形成可使

用的电路，并在ModelSim上进行验证。-For crossover design using VHDL

This paper describes the use of examples in the FPGA/CPLD design using VHDL for divider

Design, including even frequency, duty cycle and 50　of non-50　duty cycle of the odd frequency, half-integer

(N+0.5) frequency, fractional, fractional and integral crossover frequency. Can all achieve

Synplify Pro FPGA by or integrated device manufacturers an integrated, enables the formation of

With the circuit, and on the ModelSim verification.