文件名称:clk_div3
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- 上传时间:2008-10-13
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文件大小:38.51kb
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已下载:0次
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介绍说明--下载内容来自于网络,使用问题请自行百度
vhdl语言写的基数分频器,多平台,通过MODESIM仿真-vhdl language to write the base dividers, multi-platform, through simulation MODESIM
(系统自动生成,下载前可以参看下载内容)
下载文件列表
clk_div3/clk_div3.npl
clk_div3/clk_div3.vhd
clk_div3/__projnav.log
clk_div3/automake.log
clk_div3/clk_div3.prj
clk_div3/clk_div3.cmd_log
clk_div3/clk_div3.syr
clk_div3/clk_div3.lso
clk_div3/clk_div3.stx
clk_div3/clk_div3.ngr
clk_div3/clk_div3.ngc
clk_div3/pepExtractor.prj
clk_div3/clk_div3_tbw.tbw
clk_div3/clk_div3_tbw.vhw
clk_div3/clk_div3_tbw.ANT
clk_div3/clk_div3_tbw.udo
clk_div3/clk_div3_tbw.fdo
clk_div3/transcript
clk_div3/results.txt
clk_div3/vsim.wlf
clk_div3/coregen.log
clk_div3/coregen.prj
clk_div3/clk_div3.dhp
clk_div3/work/_info
clk_div3/work/clk_div3_cfg/_primary.dat
clk_div3/work/clk_div3_cfg/_vhdl.asm
clk_div3/work/clk_div3_cfg
clk_div3/work/clk_div3_tbw/_primary.dat
clk_div3/work/clk_div3_tbw/testbench_arch.dat
clk_div3/work/clk_div3_tbw/testbench_arch.asm
clk_div3/work/clk_div3_tbw
clk_div3/work/clk_div3/_primary.dat
clk_div3/work/clk_div3/behavioral.dat
clk_div3/work/clk_div3/behavioral.asm
clk_div3/work/clk_div3
clk_div3/work
clk_div3/xst/work/hdllib.ref
clk_div3/xst/work/hdpdeps.ref
clk_div3/xst/work/sub00/vhpl00.vho
clk_div3/xst/work/sub00/vhpl01.vho
clk_div3/xst/work/sub00
clk_div3/xst/work
clk_div3/xst
clk_div3/__projnav/runXst_tcl.rsp
clk_div3/__projnav/clk_div3_flowplus.gfl
clk_div3/__projnav/clk_div3.gfl
clk_div3/__projnav/clk_div3.xst
clk_div3/__projnav/hb_cmds
clk_div3/__projnav/coregen.rsp
clk_div3/__projnav
clk_div3
www.dssz.com.txt
clk_div3/clk_div3.vhd
clk_div3/__projnav.log
clk_div3/automake.log
clk_div3/clk_div3.prj
clk_div3/clk_div3.cmd_log
clk_div3/clk_div3.syr
clk_div3/clk_div3.lso
clk_div3/clk_div3.stx
clk_div3/clk_div3.ngr
clk_div3/clk_div3.ngc
clk_div3/pepExtractor.prj
clk_div3/clk_div3_tbw.tbw
clk_div3/clk_div3_tbw.vhw
clk_div3/clk_div3_tbw.ANT
clk_div3/clk_div3_tbw.udo
clk_div3/clk_div3_tbw.fdo
clk_div3/transcript
clk_div3/results.txt
clk_div3/vsim.wlf
clk_div3/coregen.log
clk_div3/coregen.prj
clk_div3/clk_div3.dhp
clk_div3/work/_info
clk_div3/work/clk_div3_cfg/_primary.dat
clk_div3/work/clk_div3_cfg/_vhdl.asm
clk_div3/work/clk_div3_cfg
clk_div3/work/clk_div3_tbw/_primary.dat
clk_div3/work/clk_div3_tbw/testbench_arch.dat
clk_div3/work/clk_div3_tbw/testbench_arch.asm
clk_div3/work/clk_div3_tbw
clk_div3/work/clk_div3/_primary.dat
clk_div3/work/clk_div3/behavioral.dat
clk_div3/work/clk_div3/behavioral.asm
clk_div3/work/clk_div3
clk_div3/work
clk_div3/xst/work/hdllib.ref
clk_div3/xst/work/hdpdeps.ref
clk_div3/xst/work/sub00/vhpl00.vho
clk_div3/xst/work/sub00/vhpl01.vho
clk_div3/xst/work/sub00
clk_div3/xst/work
clk_div3/xst
clk_div3/__projnav/runXst_tcl.rsp
clk_div3/__projnav/clk_div3_flowplus.gfl
clk_div3/__projnav/clk_div3.gfl
clk_div3/__projnav/clk_div3.xst
clk_div3/__projnav/hb_cmds
clk_div3/__projnav/coregen.rsp
clk_div3/__projnav
clk_div3
www.dssz.com.txt
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