文件名称:Altera_IP_verilog
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- 上传时间:2012-11-16
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文件大小:385.68kb
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Altera IP的产生与实现。定制一个8B10B编码器,采用verilog语言建立仿真模型,并验证。-Altera IP generation and implementation. Customize a 8B10B encoder, using verilog language, a simulation model, and verify.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Example-b4-2/Project/Simulation/220model.v
Example-b4-2/Project/Simulation/altera_mf.v
Example-b4-2/Project/Simulation/sgate.v
Example-b4-2/Project/Simulation/sim.do
Example-b4-2/Project/Simulation/wave.do
Example-b4-2/Solution/ENC.bsf
Example-b4-2/Solution/ENC.v
Example-b4-2/Solution/ENC_aot1151_enc8b10b.v
Example-b4-2/Solution/IP_ENC/ENC.bsf
Example-b4-2/Solution/IP_ENC/ENC.cmp
Example-b4-2/Solution/IP_ENC/ENC.html
Example-b4-2/Solution/IP_ENC/ENC.inc
Example-b4-2/Solution/IP_ENC/ENC.v
Example-b4-2/Solution/IP_ENC/ENC.vo
Example-b4-2/Solution/IP_ENC/ENC_aot1151_enc8b10b.ocp
Example-b4-2/Solution/IP_ENC/ENC_aot1151_enc8b10b.tcl
Example-b4-2/Solution/IP_ENC/ENC_aot1151_enc8b10b.v
Example-b4-2/Solution/IP_ENC/ENC_bb.v
Example-b4-2/Solution/IP_ENC/ENC_inst.v
Example-b4-2/Solution/IP_ENC/ENC_run_modelsim_verilog
Example-b4-2/Solution/IP_ENC/ENC_run_modelsim_vhdl
Example-b4-2/Solution/IP_ENC/ENC_simfiles.vnc
Example-b4-2/Solution/IP_ENC/ENC_tb.v
Example-b4-2/Solution/Simulation/220model.v
Example-b4-2/Solution/Simulation/altera_mf.v
Example-b4-2/Solution/Simulation/ENC.vo
Example-b4-2/Solution/Simulation/ENC_tb.v
Example-b4-2/Solution/Simulation/sgate.v
Example-b4-2/Solution/Simulation/sim.do
Example-b4-2/Solution/Simulation/wave.do
Example-b4-2/Solution/TOPIP.bdf
Example-b4-2/Solution/TOPIP.qpf
Example-b4-2/Solution/TOPIP.qsf
Example-b4-2/示例说明.doc
Example-b4-2/Solution/IP_ENC/hw/build/b0iwe
Example-b4-2/Solution/IP_ENC/hw/build
Example-b4-2/Solution/IP_ENC/iptb_ed8b10b_temp41893/simgen
Example-b4-2/Solution/IP_ENC/hw
Example-b4-2/Solution/IP_ENC/iptb_ed8b10b_temp41893
Example-b4-2/Project/IP_ENC
Example-b4-2/Project/Simulation
Example-b4-2/Solution/IP_ENC
Example-b4-2/Solution/Simulation
Example-b4-2/Project
Example-b4-2/Solution
Example-b4-2
Example-b4-2/Project/Simulation/altera_mf.v
Example-b4-2/Project/Simulation/sgate.v
Example-b4-2/Project/Simulation/sim.do
Example-b4-2/Project/Simulation/wave.do
Example-b4-2/Solution/ENC.bsf
Example-b4-2/Solution/ENC.v
Example-b4-2/Solution/ENC_aot1151_enc8b10b.v
Example-b4-2/Solution/IP_ENC/ENC.bsf
Example-b4-2/Solution/IP_ENC/ENC.cmp
Example-b4-2/Solution/IP_ENC/ENC.html
Example-b4-2/Solution/IP_ENC/ENC.inc
Example-b4-2/Solution/IP_ENC/ENC.v
Example-b4-2/Solution/IP_ENC/ENC.vo
Example-b4-2/Solution/IP_ENC/ENC_aot1151_enc8b10b.ocp
Example-b4-2/Solution/IP_ENC/ENC_aot1151_enc8b10b.tcl
Example-b4-2/Solution/IP_ENC/ENC_aot1151_enc8b10b.v
Example-b4-2/Solution/IP_ENC/ENC_bb.v
Example-b4-2/Solution/IP_ENC/ENC_inst.v
Example-b4-2/Solution/IP_ENC/ENC_run_modelsim_verilog
Example-b4-2/Solution/IP_ENC/ENC_run_modelsim_vhdl
Example-b4-2/Solution/IP_ENC/ENC_simfiles.vnc
Example-b4-2/Solution/IP_ENC/ENC_tb.v
Example-b4-2/Solution/Simulation/220model.v
Example-b4-2/Solution/Simulation/altera_mf.v
Example-b4-2/Solution/Simulation/ENC.vo
Example-b4-2/Solution/Simulation/ENC_tb.v
Example-b4-2/Solution/Simulation/sgate.v
Example-b4-2/Solution/Simulation/sim.do
Example-b4-2/Solution/Simulation/wave.do
Example-b4-2/Solution/TOPIP.bdf
Example-b4-2/Solution/TOPIP.qpf
Example-b4-2/Solution/TOPIP.qsf
Example-b4-2/示例说明.doc
Example-b4-2/Solution/IP_ENC/hw/build/b0iwe
Example-b4-2/Solution/IP_ENC/hw/build
Example-b4-2/Solution/IP_ENC/iptb_ed8b10b_temp41893/simgen
Example-b4-2/Solution/IP_ENC/hw
Example-b4-2/Solution/IP_ENC/iptb_ed8b10b_temp41893
Example-b4-2/Project/IP_ENC
Example-b4-2/Project/Simulation
Example-b4-2/Solution/IP_ENC
Example-b4-2/Solution/Simulation
Example-b4-2/Project
Example-b4-2/Solution
Example-b4-2
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