对于实现占空比为50 的N倍奇数分频，首先进行上升沿触发进行模N计数，计数到某一个值n时输出时钟进行翻转，然后再计数（N-1）/2次，再次进行翻转得到一个占空比非50 奇数n分频时钟。同理，同时进行下降沿触发的模N计数，等计数到n时，输出时钟进行翻转，同样再计数（N-1）/2次，输出时钟再次翻转生成占空比非50 的奇数n分频时钟。两个占空比非50 的n分频时钟进行相或运算，即得到占空比为50 的奇数N分频时钟。verilog HDL实现-For achieving a 50　duty cycle frequency N times the odd, the first rising edge trigger to die for N counts, count to a particular value of n, the output clock flip, and then count (N-1)/2 times Flip again to get a 50　duty cycle odd number n of non-frequency clock. Similarly, at the same time falling edge-triggered mode N counts, so count to n, the output clock flip, the same re-count (N-1)/2 times the output clock duty cycle once again turn generates 50　of non- n odd clock frequency. Two 50　duty cycle n non-frequency clock phase or operation, or get 50　duty cycle for the odd-N frequency clock.