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文件名称:vga256_success

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    2012-11-16
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    719.5kb
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介绍说明--下载内容来自于网络,使用问题请自行百度

Verilog HDL语言编写的256色VGA显示程序,引脚分配适用于21EDA的EP2C8Q208开发板

程序中的PLL分频子模块为我上传的另一代码:PLL_50MHz_to_25MHz.rar-Verilog HDL language, 256-color VGA display program, pin assignment for the 21EDA the EP2C8Q208 development board programs. The PLL frequency sub-module is in another code I uploaded: PLL_50MHz_to_25MHz.rar
(系统自动生成,下载前可以参看下载内容)

下载文件列表

vga256_success/vga256.asm.rpt
vga256_success/vga256.cdf
vga256_success/vga256.done
vga256_success/vga256.dpf
vga256_success/vga256.eda.rpt
vga256_success/vga256.fit.rpt
vga256_success/vga256.fit.smsg
vga256_success/vga256.fit.summary
vga256_success/vga256.flow.rpt
vga256_success/vga256.jic
vga256_success/vga256.map
vga256_success/vga256.map.rpt
vga256_success/vga256.map.summary
vga256_success/vga256.pin
vga256_success/vga256.pof
vga256_success/vga256.qpf
vga256_success/vga256.qsf
vga256_success/vga256.qws
vga256_success/vga256.sof
vga256_success/vga256.tan.rpt
vga256_success/vga256.tan.summary
vga256_success/vga256.v
vga256_success/vga256.v.bak
vga256_success/vga256_nativelink_simulation.rpt
vga256_success/simulation/modelsim/modelsim.ini
vga256_success/simulation/modelsim/msim_transcript
vga256_success/simulation/modelsim/vga256.sft
vga256_success/simulation/modelsim/vga256.vo
vga256_success/simulation/modelsim/vga256.vt
vga256_success/simulation/modelsim/vga256.vt.bak
vga256_success/simulation/modelsim/vga256_modelsim.xrf
vga256_success/simulation/modelsim/vga256_run_msim_rtl_verilog.do
vga256_success/simulation/modelsim/vga256_run_msim_rtl_verilog.do.bak
vga256_success/simulation/modelsim/vga256_run_msim_rtl_verilog.do.bak1
vga256_success/simulation/modelsim/vga256_run_msim_rtl_verilog.do.bak2
vga256_success/simulation/modelsim/vga256_run_msim_rtl_verilog.do.bak3
vga256_success/simulation/modelsim/vga256_v.sdo
vga256_success/simulation/modelsim/vsim.wlf
vga256_success/simulation/modelsim/rtl_work/_info
vga256_success/simulation/modelsim/rtl_work/vga_256colors/verilog.psm
vga256_success/simulation/modelsim/rtl_work/vga_256colors/_primary.dat
vga256_success/simulation/modelsim/rtl_work/vga_256colors/_primary.vhd
vga256_success/simulation/modelsim/rtl_work/vga256_vlg_tst/verilog.psm
vga256_success/simulation/modelsim/rtl_work/vga256_vlg_tst/_primary.dat
vga256_success/simulation/modelsim/rtl_work/vga256_vlg_tst/_primary.vhd
vga256_success/simulation/modelsim/rtl_work/vga256/verilog.psm
vga256_success/simulation/modelsim/rtl_work/vga256/_primary.dat
vga256_success/simulation/modelsim/rtl_work/vga256/_primary.vhd
vga256_success/simulation/modelsim/rtl_work/freq25m/verilog.psm
vga256_success/simulation/modelsim/rtl_work/freq25m/_primary.dat
vga256_success/simulation/modelsim/rtl_work/freq25m/_primary.vhd
vga256_success/incremental_db/README
vga256_success/incremental_db/compiled_partitions/vga256.root_partition.cmp.atm
vga256_success/incremental_db/compiled_partitions/vga256.root_partition.cmp.dfp
vga256_success/incremental_db/compiled_partitions/vga256.root_partition.cmp.hdbx
vga256_success/incremental_db/compiled_partitions/vga256.root_partition.cmp.kpt
vga256_success/incremental_db/compiled_partitions/vga256.root_partition.cmp.logdb
vga256_success/incremental_db/compiled_partitions/vga256.root_partition.cmp.rcf
vga256_success/incremental_db/compiled_partitions/vga256.root_partition.map.atm
vga256_success/incremental_db/compiled_partitions/vga256.root_partition.map.dpi
vga256_success/incremental_db/compiled_partitions/vga256.root_partition.map.hdbx
vga256_success/incremental_db/compiled_partitions/vga256.root_partition.map.kpt
vga256_success/incremental_db/compiled_partitions/vga256.root_partition.merge_hb.atm
vga256_success/db/prev_cmp_vga256.asm.qmsg
vga256_success/db/prev_cmp_vga256.eda.qmsg
vga256_success/db/prev_cmp_vga256.fit.qmsg
vga256_success/db/prev_cmp_vga256.map.qmsg
vga256_success/db/prev_cmp_vga256.qmsg
vga256_success/db/prev_cmp_vga256.tan.qmsg
vga256_success/db/vga256.(0).cnf.cdb
vga256_success/db/vga256.(0).cnf.hdb
vga256_success/db/vga256.(1).cnf.cdb
vga256_success/db/vga256.(1).cnf.hdb
vga256_success/db/vga256.(2).cnf.cdb
vga256_success/db/vga256.(2).cnf.hdb
vga256_success/db/vga256.(3).cnf.cdb
vga256_success/db/vga256.(3).cnf.hdb
vga256_success/db/vga256.ace_cmp.bpm
vga256_success/db/vga256.ace_cmp.cdb
vga256_success/db/vga256.ace_cmp.ecobp
vga256_success/db/vga256.ace_cmp.hdb
vga256_success/db/vga256.asm.qmsg
vga256_success/db/vga256.asm_labs.ddb
vga256_success/db/vga256.atom_map.rvd
vga256_success/db/vga256.cbx.xml
vga256_success/db/vga256.cmp.bpm
vga256_success/db/vga256.cmp.cdb
vga256_success/db/vga256.cmp.ecobp
vga256_success/db/vga256.cmp.hdb
vga256_success/db/vga256.cmp.kpt
vga256_success/db/vga256.cmp.logdb
vga256_success/db/vga256.cmp.rdb
vga256_success/db/vga256.cmp.tdb
vga256_success/db/vga256.cmp0.ddb
vga256_success/db/vga256.cmp2.ddb
vga256_success/db/vga256.cmp_merge.kpt
vga256_success/db/vga256.db_info
vga256_success/db/vga256.eco.cdb
vga256_success/db/vga256.eda.qmsg
vga256_success/db/vga256.fit.qmsg
vga256_success/db/vga256.hier_info
vga256_success/db/vga256.hif
vga256_success/db/vga256.lpc.html
vga256_success/db/vga256.lpc.rdb
vga256_success/db/vga256.lpc.txt
vga256_success/db/vga256.map.bpm
vga256_success/db/vga256.map.cdb
vga256_success/db/vga256.map.ecobp
vga256_success/db/vga256.map.hdb
vga256_success/db/vga256.map.kpt
vga256_success/db/vga256.map.logdb
vga256_success/db/vga256.map.qmsg
vga256_success/db/vga256.map_bb.cdb
vga256_success/db/vga256.map_bb.hdb
vga256_success/db/vga256.ma

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