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I2C/design/I2CSlave.prj
I2C/design/I2Cslave.v
I2C/design/myram.v
I2C/design/rev_1/.recordref
I2C/design/rev_1/AutoConstraint_I2Cslave.sdc
I2C/design/rev_1/AutoConstraint_myRAM.sdc
I2C/design/rev_1/I2Cslave.edf
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I2C/design/rev_1/I2Cslave.srr
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I2C/design/rev_1/syntmp/myram.msg
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I2C/design/rev_1/timescale.srr
I2C/design/rev_1/traplog.tlg
I2C/design/rev_1/verif/I2Cslave.vif
I2C/design/rev_1/verif/myram.vif
I2C/design/rev_1/verif/slave_top.vif
I2C/design/rev_1/verif
I2C/design/rev_1
I2C/design/sim/all.do
I2C/design/sim/i2c_master_bit_ctrl.v
I2C/design/sim/i2c_master_byte_ctrl.v
I2C/design/sim/i2c_master_defines.v
I2C/design/sim/i2c_master_top.v
I2C/design/sim/Sim_Behav.bat
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I2C/design/sim/transcript
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I2C/design/sim/work/@i2@cslave
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I2C/design/sim/work/i2c_master_bit_ctrl
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I2C/design/sim/work/i2c_master_byte_ctrl
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I2C/design/sim/work/tst_bench_top/verilog.asm
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I2C/design/syntmp.msg
I2C/design/test.prd
I2C/design/test.prj
I2C/design
I2C/I2C Slave设计笔记.doc
I2C