74hc4017/
74hc4017/component/
74hc4017/constraint/
74hc4017/coreconsole/
74hc4017/designer/
74hc4017/designer/impl1/
74hc4017/designer/impl1/model4017.dtf/
74hc4017/designer/impl1/model4017_fp/
74hc4017/designer/impl1/model4017_fp/projectData/
74hc4017/designer/impl1/simulation/
74hc4017/designer/impl1/simulation/postlayout/
74hc4017/designer/impl1/simulation/postlayout/model4017/
74hc4017/designer/impl1/simulation/postlayout/stimulus/
74hc4017/designer/impl1/simulation/postlayout/tb_clock_minmax/
74hc4017/designer/impl1/simulation/postlayout/testbench/
74hc4017/designer/impl1/simulation/postlayout/_temp/
74hc4017/hdl/
74hc4017/phy_synthesis/
74hc4017/simulation/
74hc4017/simulation/postsynth/
74hc4017/simulation/postsynth/model4017/
74hc4017/simulation/postsynth/stimulus/
74hc4017/simulation/postsynth/tb_clock_minmax/
74hc4017/simulation/postsynth/testbench/
74hc4017/simulation/postsynth/_temp/
74hc4017/simulation/presynth/
74hc4017/simulation/presynth/model/
74hc4017/simulation/presynth/model4017/
74hc4017/simulation/presynth/stimulus/
74hc4017/simulation/presynth/tb_clock_minmax/
74hc4017/simulation/presynth/testbench/
74hc4017/simulation/presynth/_temp/
74hc4017/smartgen/
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74hc4017/synthesis/
74hc4017/synthesis/backup/
74hc4017/synthesis/coreip/
74hc4017/synthesis/syntmp/
74hc4017/viewdraw/
74hc4017/viewdraw/sch/
74hc4017/viewdraw/sym/
74hc4017/viewdraw/vf/
74hc4017/viewdraw/wir/
74hc4017/4017_module.prj
74hc4017/designer/impl1/4017model.ide_des
74hc4017/designer/impl1/4017_module.ide_des
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74hc4017/designer/impl1/designer_synth_check.log
74hc4017/designer/impl1/model.ide_des
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74hc4017/designer/impl1/model4017.dtf/verify.log
74hc4017/designer/impl1/model4017.ide_des
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74hc4017/designer/impl1/model4017.tcl
74hc4017/designer/impl1/model4017_ba.sdf
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74hc4017/designer/impl1/model4017_ba.v
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74hc4017/designer/impl1/model4017_fp/model4017.log
74hc4017/designer/impl1/model4017_fp/model4017.pro
74hc4017/designer/impl1/model4017_fp/projectData/model4017.pdb
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74hc4017/simulation/postsynth/model4017/verilog.psm
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74hc4017/simulation/postsynth/tb_clock_minmax/_primary.vhd
74hc4017/simulation/postsynth/testbench/verilog.psm
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74hc4017/