文件名称:pwm_timer
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- 上传时间:2012-11-16
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文件大小:265.07kb
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PWM和Timer的FPGA实现,文档代码齐全。-PWM and Timer for FPGA implementation, documentation, code complete.
相关搜索: vhdl pwm
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ptc
ptc/bench
ptc/bench/CVS
ptc/bench/CVS/Entries
ptc/bench/CVS/Repository
ptc/bench/CVS/Root
ptc/bench/verilog
ptc/bench/verilog/clkrst.v
ptc/bench/verilog/CVS
ptc/bench/verilog/CVS/Entries
ptc/bench/verilog/CVS/Repository
ptc/bench/verilog/CVS/Root
ptc/bench/verilog/tb_defines.v
ptc/bench/verilog/tb_tasks.v
ptc/bench/verilog/tb_top.v
ptc/bench/verilog/timescale.v
ptc/bench/verilog/wb_master.v
ptc/bench/VHDL
ptc/bench/VHDL/CVS
ptc/bench/VHDL/CVS/Entries
ptc/bench/VHDL/CVS/Repository
ptc/bench/VHDL/CVS/Root
ptc/CVS
ptc/CVS/Entries
ptc/CVS/Repository
ptc/CVS/Root
ptc/doc
ptc/doc/CVS
ptc/doc/CVS/Entries
ptc/doc/CVS/Repository
ptc/doc/CVS/Root
ptc/doc/ptc_spec.pdf
ptc/doc/src
ptc/doc/src/CVS
ptc/doc/src/CVS/Entries
ptc/doc/src/CVS/Repository
ptc/doc/src/CVS/Root
ptc/doc/src/ptc_spec.doc
ptc/fv
ptc/fv/CVS
ptc/fv/CVS/Entries
ptc/fv/CVS/Repository
ptc/fv/CVS/Root
ptc/lint
ptc/lint/bin
ptc/lint/bin/CVS
ptc/lint/bin/CVS/Entries
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ptc/lint/log
ptc/lint/log/CVS
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ptc/lint/log/CVS/Repository
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ptc/lint/out
ptc/lint/out/CVS
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ptc/lint/run
ptc/lint/run/CVS
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ptc/rtl
ptc/rtl/CVS
ptc/rtl/CVS/Entries
ptc/rtl/CVS/Repository
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ptc/rtl/verilog
ptc/rtl/verilog/CVS
ptc/rtl/verilog/CVS/Entries
ptc/rtl/verilog/CVS/Repository
ptc/rtl/verilog/CVS/Root
ptc/rtl/verilog/ptc_defines.v
ptc/rtl/verilog/ptc_top.v
ptc/rtl/VHDL
ptc/rtl/VHDL/CVS
ptc/rtl/VHDL/CVS/Entries
ptc/rtl/VHDL/CVS/Repository
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ptc/sim
ptc/sim/CVS
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ptc/sim/gate_sim
ptc/sim/gate_sim/bin
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ptc/sim/rtl_sim
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ptc/sim/rtl_sim/bin/sim.sh
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ptc/sim/rtl_sim/run
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ptc/sim/rtl_sim/src
ptc/sim/rtl_sim/src/CVS
ptc/sim/rtl_sim/src/CVS/Entries
ptc/sim/rtl_sim/src/CVS/Repository
ptc/sim/rtl_sim/src/CVS/Root
ptc/syn
ptc/syn/bin
ptc/syn/bin/cons_art_umc18.inc
ptc/syn/bin/cons_vs_umc18.inc
ptc/syn/bin/CVS
ptc/syn/bin/CVS/Entries
ptc/syn/bin/CVS/Repository
ptc/syn/bin/CVS/Root
ptc/syn/bin/read_design.inc
ptc/syn/bin/reports.inc
ptc/syn/bin/save_design.inc
ptc/syn/bin/select_tech.inc
ptc/syn/bin/set_env.inc
ptc/syn/bin/tech_art_umc18.inc
ptc/syn/bin/tech_vs_umc18.inc
ptc/syn/bin/top_ptc.scr
ptc/syn/CVS
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ptc/bench/verilog
ptc/bench/verilog/clkrst.v
ptc/bench/verilog/CVS
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ptc/bench/verilog/CVS/Repository
ptc/bench/verilog/CVS/Root
ptc/bench/verilog/tb_defines.v
ptc/bench/verilog/tb_tasks.v
ptc/bench/verilog/tb_top.v
ptc/bench/verilog/timescale.v
ptc/bench/verilog/wb_master.v
ptc/bench/VHDL
ptc/bench/VHDL/CVS
ptc/bench/VHDL/CVS/Entries
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ptc/CVS
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ptc/doc/CVS/Root
ptc/doc/ptc_spec.pdf
ptc/doc/src
ptc/doc/src/CVS
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ptc/lint/run
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ptc/rtl/verilog/ptc_defines.v
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ptc/rtl/VHDL
ptc/rtl/VHDL/CVS
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ptc/syn
ptc/syn/bin
ptc/syn/bin/cons_art_umc18.inc
ptc/syn/bin/cons_vs_umc18.inc
ptc/syn/bin/CVS
ptc/syn/bin/CVS/Entries
ptc/syn/bin/CVS/Repository
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ptc/syn/bin/read_design.inc
ptc/syn/bin/reports.inc
ptc/syn/bin/save_design.inc
ptc/syn/bin/select_tech.inc
ptc/syn/bin/set_env.inc
ptc/syn/bin/tech_art_umc18.inc
ptc/syn/bin/tech_vs_umc18.inc
ptc/syn/bin/top_ptc.scr
ptc/syn/CVS
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