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文件名称:LabDesign

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.06mb
  • 已下载：
    0次
  • 提 供 者：
    a****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

A Nice Lab Design Contains Different Implementations to different logic functionalistsand simulation to PIC16F84A using Verilog-A Nice Lab Design Contains Different Implementations to different logic functionalistsand simulation to PIC16F84A using Verilog　　
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Exp 7/Data Memory/Data memory.dsk
Exp 7/Data Memory/Data memory.hpj
Exp 7/Data Memory/Data.BU
Exp 7/Data Memory/Data.v
Exp 7/Data Memory/GPRs.v
Exp 7/Data Memory/Lib439.BU
Exp 7/Data Memory/Lib439.v
Exp 7/Data Memory/Mux21.v
Exp 7/Data Memory/Mux217.v
Exp 7/Data Memory/PA.BU
Exp 7/Data Memory/PA.v
Exp 7/Data Memory/PB.v
Exp 7/Data Memory/Register.BU
Exp 7/Data Memory/Register.v
Exp 7/Data Memory/Register5.BU
Exp 7/Data Memory/Register5.v
Exp 7/Data Memory/Status.BU
Exp 7/Data Memory/Status.v
Exp 7/Data Memory/T5.v
Exp 7/Data Memory/T8.v
Exp 7/Data Memory/test.BU
Exp 7/Data Memory/test.v
Exp 7/Data Memory/Tri5.v
Exp 7/Data Memory/Tri8.BU
Exp 7/Data Memory/Tri8.v
Exp 7/Data Memory/untitled.dsk
Exp 7/Data Memory/untitled0.BU
Exp 7/Data Memory/verilog.key
Exp 7/Data Memory/verilog.log
Exp 7/Data Memory/waveperl.log
Exp 7/Thumbs.db
Exp 8/ALU.BU
Exp 8/ALU.v
Exp 8/ALURipple.v
Exp 8/Bit.BU
Exp 8/Bit.v
Exp 8/control.BU
Exp 8/control.v
Exp 8/Data.v
Exp 8/Datapath.v
Exp 8/Dec.v
Exp 8/Dec2to4.v
Exp 8/Dec2to4E.v
Exp 8/Dec3to8.v
Exp 8/Flash.v
Exp 8/FullAdder.v
Exp 8/GPRs.v
Exp 8/INC.v
Exp 8/INCPC.v
Exp 8/IR.v
Exp 8/Lib439.v
Exp 8/Logic.BU
Exp 8/Logic.v
Exp 8/Mem.v
Exp 8/Move.BU
Exp 8/Move.v
Exp 8/Mux21.v
Exp 8/Mux217.v
Exp 8/Mux2t18bit.v
Exp 8/Mux4t110bit.v
Exp 8/Mux4t13bit.v
Exp 8/Mux4t18bit.BU
Exp 8/Mux4t18bit.v
Exp 8/Mux4t18bitone.BU
Exp 8/Mux4t18bitone.v
Exp 8/Mux4to1.BU
Exp 8/Mux4to1.v
Exp 8/Mux4to1one sline.v
Exp 8/Mux81.BU
Exp 8/Mux81.v
Exp 8/PA.v
Exp 8/PB.v
Exp 8/PC.v
Exp 8/proc.BU
Exp 8/proc.v
Exp 8/Processor.dsk
Exp 8/Processor.hpj
Exp 8/ProgMem.v
Exp 8/Register.v
Exp 8/Register5.v
Exp 8/Sp.v
Exp 8/Stack.v
Exp 8/Status.v
Exp 8/T5.v
Exp 8/T8.v
Exp 8/Tri5.v
Exp 8/Tri8.v
Exp 8/untitled.dsk
Exp 8/verilog.key
Exp 8/verilog.log
Exp 8/waveperl.log
Exp 1/Exp 1/Counter/Counter.dsk
Exp 1/Exp 1/Counter/Counter.hpj
Exp 1/Exp 1/Counter/Counter3bit.BU
Exp 1/Exp 1/Counter/Counter3bit.v
Exp 1/Exp 1/Counter/Lib439.BU
Exp 1/Exp 1/Counter/Lib439.v
Exp 1/Exp 1/Counter/test.BU
Exp 1/Exp 1/Counter/test.v
Exp 1/Exp 1/Counter/TFF.v
Exp 1/Exp 1/Counter/untitled.dsk
Exp 1/Exp 1/Counter/verilog.key
Exp 1/Exp 1/Counter/verilog.log
Exp 1/Exp 1/Counter/waveperl.log
Exp 1/Exp 1/Function/Function.BU
Exp 1/Exp 1/Function/Function.dsk
Exp 1/Exp 1/Function/Function.hpj
Exp 1/Exp 1/Function/Function.v
Exp 1/Exp 1/Function/Lib439.BU
Exp 1/Exp 1/Function/Lib439.v
Exp 1/Exp 1/Function/test.BU
Exp 1/Exp 1/Function/test.v
Exp 1/Exp 1/Function/untitled.dsk
Exp 1/Exp 1/Function/verilog.key
Exp 1/Exp 1/Function/verilog.log
Exp 1/Exp 1/Function/waveperl.log
Exp 2/Ideal Simulation No Delay/ALU CLA/ALU.BU
Exp 2/Ideal Simulation No Delay/ALU CLA/ALU.dsk
Exp 2/Ideal Simulation No Delay/ALU CLA/ALU.hpj
Exp 2/Ideal Simulation No Delay/ALU CLA/ALU.v
Exp 2/Ideal Simulation No Delay/ALU CLA/CLA.BU
Exp 2/Ideal Simulation No Delay/ALU CLA/CLA.v
Exp 2/Ideal Simulation No Delay/ALU CLA/Lib439.v
Exp 2/Ideal Simulation No Delay/ALU CLA/Mux21.v
Exp 2/Ideal Simulation No Delay/ALU CLA/test.v
Exp 2/Ideal Simulation No Delay/ALU CLA/untitled.dsk
Exp 2/Ideal Simulation No Delay/ALU CLA/verilog.key
Exp 2/Ideal Simulation No Delay/ALU CLA/verilog.log
Exp 2/Ideal Simulation No Delay/ALU CLA/waveperl.log
Exp 2/Ideal Simulation No Delay/ALU Ripple/ALU Ripple.dsk
Exp 2/Ideal Simulation No Delay/ALU Ripple/ALU Ripple.hpj
Exp 2/Ideal Simulation No Delay/ALU Ripple/ALURipple.BU
Exp 2/Ideal Simulation No Delay/ALU Ripple/ALURipple.v
Exp 2/Ideal Simulation No Delay/ALU Ripple/FullAdder.v
Exp 2/Ideal Simulation No Delay/ALU Ripple/Lib439.v
Exp 2/Ideal Simulation No Delay/ALU Ripple/Mux21.v
Exp 2/Ideal Simulation No Delay/ALU Ripple/test.BU
Exp 2/Ideal Simulation No Delay/ALU Ripple/test.v
Exp 2/Ideal Simulation No Delay/ALU Ripple/untitled.dsk
Exp 2/Ideal Simulation No Delay/ALU Ripple/verilog.key
Exp 2/Ideal Simulation No Delay/ALU Ripple/verilog.log
Exp 2/Ideal Simulation No Delay/ALU Ripple/waveperl.log
Exp 2/Ideal Simulation No Delay/Full Adder/Full Adder.dsk
Exp 2/Ideal Simulation No Delay/Full Adder/Full Adder.hpj
Exp 2/Ideal Simulation No Delay/Full Adder/FullAdder.v
Exp 2/Ideal Simulation No Delay/Full Adder/Lib439.BU
Exp 2/Ideal Simulation No Delay/Full Adder/Lib439.v
Exp 2/Ideal Simulation No Delay/Full Adder/test.BU
Exp 2/Ideal Simulation No Delay/Full Adder/test.v
Exp 2/Ideal Simulation No Delay/Full Adder/untitled.dsk
Exp 2/Ideal Simulation No Delay/Full Adder/verilog.BU
Exp 2/Ideal Simulation No Delay/Full Adder/verilog.key
Exp 2/Ideal Simulation No Delay/Full Adder/verilog.log
Exp 2/Ideal Simulation No Delay/Full Adder/waveperl.log
Exp 2/Ideal Simulation No Delay/LookAhead Adder/CLA.BU
Exp 2/Ideal Simulation No Delay/LookAhead Adder/CLA.v
Exp 2/Ideal Simulation No Delay/LookAhead Adder/Lib439.v
Exp 2/Ideal Simulation No Delay/LookAhead Adder/LookAhead.dsk
Exp 2/Ideal Simulation No Delay/LookAhead Adder/LookAhead.hpj
Exp 2/Ideal Simulation No Delay/LookAhead Adder/test.BU
Exp 2/Ideal Simulation No Delay/LookAhead Adder/test.v
Exp 2/Ideal Simulation No Delay/LookAhead Adder/untitled.dsk
Exp 2/Ideal Simulation No Delay/LookAhead Adder/verilog.key
Exp 2/Ideal Simulation No Delay/LookAhead Adde

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