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文件名称:spdmeasure

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  • 上传时间:
    2012-11-16
  • 文件大小:
    22.84mb
  • 已下载:
    2次
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介绍说明--下载内容来自于网络,使用问题请自行百度

脉冲测速,用VERILOG语言实现,自动跳档-Pulse velocity, with the VERILOG language, automatically skip files
(系统自动生成,下载前可以参看下载内容)

下载文件列表

sac/component/work/aa/aa.cxf
sac/component/work/aa/aa.sdb
sac/component/work/iobuf/iobuf.cxf
sac/component/work/iobuf/iobuf.sdb
sac/component/work/IO_BUF/IO_BUF.cxf
sac/component/work/IO_BUF/IO_BUF.sdb
sac/component/work/sac/sac.cxf
sac/component/work/sac/sac.sdb
sac/constraint/data/sac_con.pdc.ce
sac/constraint/data/sac_con.pdc.lce
sac/constraint/sac_con.pdc
sac/cpu_main.v
sac/designer/impl1/ada01332-1.tmp
sac/designer/impl1/af0.ini
sac/designer/impl1/ccc.ide_des
sac/designer/impl1/designer.log
sac/designer/impl1/designer_synth_check.log
sac/designer/impl1/freaquency_measure.ide_des
sac/designer/impl1/iobuf.ide_des
sac/designer/impl1/IO_BUF.ide_des
sac/designer/impl1/newCore.ide_des
sac/designer/impl1/phase_measure.ide_des
sac/designer/impl1/PLL2.ide_des
sac/designer/impl1/PLLMUL2.ide_des
sac/designer/impl1/pluse_count.ide_des
sac/designer/impl1/sac_top.adb
sac/designer/impl1/sac_top.dtf/verify.log
sac/designer/impl1/sac_top.ide_des
sac/designer/impl1/sac_top.lok
sac/designer/impl1/sac_top.pdb
sac/designer/impl1/sac_top.pdb.depends
sac/designer/impl1/sac_top.stp
sac/designer/impl1/sac_top.tcl
sac/designer/impl1/sac_top_ba.sdf
sac/designer/impl1/sac_top_ba.v
sac/designer/impl1/sac_top_fp/$$FlashPro_08456.L$$
sac/designer/impl1/sac_top_fp/projectData/sac_top.stp
sac/designer/impl1/sac_top_fp/sac_top.log
sac/designer/impl1/sac_top_fp/sac_top.pro
sac/designer/impl2/designer.log
sac/designer/impl2/freaquency_measure.ide_des
sac/designer/impl2/iobuf.ide_des
sac/designer/impl2/IO_BUF.ide_des
sac/designer/impl2/newCore.ide_des
sac/designer/impl2/phase_measure.ide_des
sac/designer/impl2/pluse_count.ide_des
sac/designer/impl2/sac_top.adb
sac/designer/impl2/sac_top.dtf/verify.log
sac/designer/impl2/sac_top.ide_des
sac/designer/impl2/sac_top.pdb
sac/designer/impl2/sac_top.pdb.depends
sac/designer/impl2/sac_top.stp
sac/designer/impl2/sac_top.tcl
sac/designer/sac_top.stp
sac/hdl/freaquency_measure.v
sac/hdl/phase_measure.v
sac/hdl/pluse_count.v
sac/hdl/sac_top.v
sac/hdl/waveperl.log
sac/hdl.rar
sac/pluse_count.v
sac/sac.prj
sac/simulation/modelsim.ini
sac/simulation/modelsim.ini.sav
sac/simulation/modelsim.log
sac/simulation/presynth/@i@o@b@u@f/verilog.psm
sac/simulation/presynth/@i@o@b@u@f/_primary.dat
sac/simulation/presynth/@i@o@b@u@f/_primary.dbs
sac/simulation/presynth/@i@o@b@u@f/_primary.vhd
sac/simulation/presynth/@p@l@l@m@u@l2/verilog.psm
sac/simulation/presynth/@p@l@l@m@u@l2/_primary.dat
sac/simulation/presynth/@p@l@l@m@u@l2/_primary.dbs
sac/simulation/presynth/@p@l@l@m@u@l2/_primary.vhd
sac/simulation/presynth/phase_measure/verilog.psm
sac/simulation/presynth/phase_measure/_primary.dat
sac/simulation/presynth/phase_measure/_primary.dbs
sac/simulation/presynth/phase_measure/_primary.vhd
sac/simulation/presynth/_info
sac/simulation/presynth/_temp/vlog29nxnm
sac/simulation/presynth/_temp/vlog2shx6q
sac/simulation/presynth/_temp/vlog9e45z8
sac/simulation/presynth/_temp/vlogdzxibe
sac/simulation/presynth/_vmake
sac/simulation/run.do
sac/smartgen/ccc/ccc.cxf
sac/smartgen/ccc/ccc.gen
sac/smartgen/ccc/ccc.log
sac/smartgen/ccc/ccc.v
sac/smartgen/IOBUF/IOBUF.cxf
sac/smartgen/IOBUF/IOBUF.gen
sac/smartgen/IOBUF/IOBUF.log
sac/smartgen/IOBUF/IOBUF.v
sac/smartgen/IOBUF_work.ixf
sac/smartgen/PLL2/PLL2.cxf
sac/smartgen/PLL2/PLL2.gen
sac/smartgen/PLL2/PLL2.log
sac/smartgen/PLL2/PLL2.v
sac/smartgen/PLL2_work.ixf
sac/smartgen/PLLMUL2/PLLMUL2.cxf
sac/smartgen/PLLMUL2/PLLMUL2.gen
sac/smartgen/PLLMUL2/PLLMUL2.log
sac/smartgen/PLLMUL2/PLLMUL2.v
sac/smartgen/sac_work.ixf
sac/smartgen/smartgen.aws
sac/stimulus/BtimErrors.log
sac/stimulus/files_to_build.txt
sac/stimulus/sac_top.dsk
sac/stimulus/sac_top.hpj
sac/stimulus/waveperl.log
sac/synthesis/.recordref
sac/synthesis/backup/sac_top.srr
sac/synthesis/genpkg0a04192
sac/synthesis/gentmp0a04192
sac/synthesis/logtmp0a04192
sac/synthesis/run_options.txt
sac/synthesis/sac_top.areasrr
sac/synthesis/sac_top.edn
sac/synthesis/sac_top.map
sac/synthesis/sac_top.pdc
sac/synthesis/sac_top.sdf
sac/synthesis/sac_top.so
sac/synthesis/sac_top.srd
sac/synthesis/sac_top.srm
sac/synthesis/sac_top.srr
sac/synthesis/sac_top.srs
sac/synthesis/sac_top.szr
sac/synthesis/sac_top.tlg
sac/synthesis/sac_top.v
sac/synthesis/sac_top_sdc.sdc
sac/synthesis/sac_top_syn.prd
sac/synthesis/sac_top_syn.prj
sac/synthesis/stdout.log
sac/synthesis/syng0a04192
sac/synthesis/syntmp/sac_top.plg
sac/synthesis/traplog.tlg
sac/synthesis/vhdlsyn0a04192
sac/viewdraw/sym/IOBUF.1
sac/viewdraw/sym/sac_top.1
sac/viewdraw/vf/project.lst
sac/viewdraw/viewdraw.ini
sac/waveperl.log
sac/designer/impl1/sac_top_fp/projectData
sac/component/work/aa
sac/component/work/iobuf
sac/component/work/IO_BUF
sac/component/work/sac
sac/designer/impl1/sac_top.dtf
sac/designer/impl1/sac_top_fp
sac/designer/impl1/simulation
sac/designer/impl2/sac_top.dtf
sac/designer/impl2/simulation
sac/simulation/presynth/@i@o@b@u@f
sac/simulation/presynth/@p@l@l@m@u@l2
sac/simulation/presynth/phase_measure
sac/simulation/presynth/_temp
sac/viewdraw/sch/bac
sac/viewdraw/sch/lock
sac/viewdraw/sch/sav
sac/viewdraw/sym/bac
sac/viewdraw/sym/sav
sac/viewdraw/wir/bac
sac/viewdraw/wir/sav
sac/comp

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