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文件名称:LIP1122CORE_irpwm

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  • 上传时间:
    2012-11-16
  • 文件大小:
    455.02kb
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介绍说明--下载内容来自于网络,使用问题请自行百度

Verilog PWM code module
(系统自动生成,下载前可以参看下载内容)

下载文件列表

LIP1122CORE_irpwn.doc
CVS/Entries
CVS/Repository
CVS/Root
hdl/irpwm_ir_nec.v
hdl/irpwm_ir_rc5.v
hdl/irpwm_pwm.v
hdl/CVS/Entries
hdl/CVS/Repository
hdl/CVS/Root
PWM_1/.untf
PWM_1/automake.log
PWM_1/irpwm.v
PWM_1/irpwm_ir_nec.bld
PWM_1/irpwm_ir_nec.cel
PWM_1/irpwm_ir_nec.cmd_log
PWM_1/irpwm_ir_nec.lso
PWM_1/irpwm_ir_nec.ngc
PWM_1/irpwm_ir_nec.ngd
PWM_1/irpwm_ir_nec.ngr
PWM_1/irpwm_ir_nec.prj
PWM_1/irpwm_ir_nec.stx
PWM_1/irpwm_ir_nec.syr
PWM_1/irpwm_ir_nec.ucf
PWM_1/irpwm_ir_nec.v
PWM_1/irpwm_ir_nec_summary.html
PWM_1/irpwm_ir_nec_vhdl.prj
PWM_1/irpwm_ir_rc5.v
PWM_1/irpwm_pwm.v
PWM_1/irpwm_summary.html
PWM_1/Project.dhp
PWM_1/PWM_1.dhp
PWM_1/PWM_1.ise
PWM_1/PWM_1.ise_ISE_Backup
PWM_1/__projnav.log
PWM_1/__projnav/ednTOngd_tcl.rsp
PWM_1/__projnav/irpwm_ir_nec.xst
PWM_1/__projnav/parentCreateTimingConstraintsApp_tcl.rsp
PWM_1/__projnav/PWM_1.gfl
PWM_1/__projnav/PWM_1_flowplus.gfl
PWM_1/__projnav/runXst_tcl.rsp
PWM_1/__projnav/sumrpt_tcl.rsp
PWM_1/_ngo/netlist.lst
PWM_1/xst/work/hdllib.ref
PWM_1/xst/work/vlg5A/irpwm__ir__nec.bin
syn/CVS/Entries
syn/CVS/Repository
syn/CVS/Root
syn/artisan_tsmc15lv/.cvsignore
syn/artisan_tsmc15lv/irpwm_extract_netlist.tcl
syn/artisan_tsmc15lv/irpwm_formal_verif.tcl
syn/artisan_tsmc15lv/irpwm_report.tcl
syn/artisan_tsmc15lv/irpwm_setup.tcl
syn/artisan_tsmc15lv/irpwm_simple_compile.tcl
syn/artisan_tsmc15lv/Makefile
syn/artisan_tsmc15lv/work_lib/irpwm%verilog.syn
syn/artisan_tsmc15lv/work_lib/irpwm%verilog__verilog.syn
syn/artisan_tsmc15lv/work_lib/IRPWM.mr
syn/artisan_tsmc15lv/work_lib/irpwm_ir_nec%verilog.syn
syn/artisan_tsmc15lv/work_lib/irpwm_ir_nec%verilog__verilog.syn
syn/artisan_tsmc15lv/work_lib/IRPWM_IR_NEC.mr
syn/artisan_tsmc15lv/work_lib/irpwm_ir_rc5%verilog.syn
syn/artisan_tsmc15lv/work_lib/irpwm_ir_rc5%verilog__verilog.syn
syn/artisan_tsmc15lv/work_lib/IRPWM_IR_RC5.mr
syn/artisan_tsmc15lv/work_lib/irpwm_pwm%verilog.syn
syn/artisan_tsmc15lv/work_lib/irpwm_pwm%verilog__verilog.syn
syn/artisan_tsmc15lv/work_lib/IRPWM_PWM.mr
syn/artisan_tsmc15lv/synthesis/irpwm.db
syn/artisan_tsmc15lv/synthesis/irpwm.v
syn/artisan_tsmc15lv/synthesis/irpwm_area.rpt
syn/artisan_tsmc15lv/synthesis/irpwm_cell.rpt
syn/artisan_tsmc15lv/synthesis/irpwm_constraint.rpt
syn/artisan_tsmc15lv/synthesis/irpwm_net.rpt
syn/artisan_tsmc15lv/synthesis/irpwm_qor.rpt
syn/artisan_tsmc15lv/synthesis/irpwm_timing.rpt
syn/artisan_tsmc15lv/CVS/Entries
syn/artisan_tsmc15lv/CVS/Repository
syn/artisan_tsmc15lv/CVS/Root
irpwm.v
PWM_1/xst/dump.xst/irpwm_ir_nec.prj/ngx/opt
PWM_1/xst/dump.xst/irpwm_ir_nec.prj/ngx/notopt
PWM_1/xst/dump.xst/irpwm_ir_nec.prj/ngx
PWM_1/xst/work/vlg5A
PWM_1/xst/dump.xst/irpwm_ir_nec.prj
PWM_1/xst/work
PWM_1/xst/dump.xst
syn/artisan_tsmc15lv/work_lib
syn/artisan_tsmc15lv/synthesis
syn/artisan_tsmc15lv/CVS
hdl/CVS
PWM_1/__projnav
PWM_1/_xmsgs
PWM_1/_ngo
PWM_1/xst
syn/CVS
syn/artisan_tsmc15lv
CVS
hdl
PWM_1
syn

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