3.设计一个数据宽度8bit，深度是16的异步FIFO（读写时钟不相同），

当读写时钟的频率分别为wrclk＝40MHz、rdclk＝20MHz时，仿真其逻辑波形。25,50

当读时钟比写时钟快时（wrclk＝20MHz，rdclk＝40MHz），

如何保证读出的数据是写进去的有效数据？仿真验证你的设计。

对比第3题的同步FIFO，分析同步FIFO和异步FIFO的不同特性。-3. To design a data width of 8bit, depth is 16 asynchronous FIFO (read and write clock is not the same), when read and write clock frequencies were wrclk = 40MHz, rdclk = 20MHz, the simulation of the logic waveform. 25,50 When the time clock is faster than write clock time (wrclk = 20MHz, rdclk = 40MHz), how to ensure that read data is written into the valid data? Simulation of your design. Question 3 of the synchronization compared FIFO, analysis of synchronous and asynchronous FIFO FIFO different characteristics.