文件名称:da
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- 上传时间:2012-11-16
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文件大小:210.07kb
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FIR滤波器利用串行DA算法实现16阶的,直接可用 ,用VHDL编程-Serial DA FIR filter algorithm using 16 bands, directly available, VHDL programming
(系统自动生成,下载前可以参看下载内容)
下载文件列表
da/adder_mac.v
da/ctrl_all.v
da/dacase8_1.v
da/dacase8_2.v
da/da_fir.prd
da/da_fir.prj
da/da_fir.qpf
da/DA_top.cr.mti
da/DA_top.mpf
da/DA_top.v
da/matlab_sim/fir_da.m
da/matlab_sim/fir_da_tb.m
da/matlab_sim/gencase.m
da/MUX_16X1_M.v
da/Q_258_0_15_0_.mif
da/Q_258_0_15_0_mif1.mif
da/readme.txt
da/rev_3/AutoConstraint_DA_top.sdc
da/rev_3/MUX_16X1_M.fse
da/rev_3/MUX_16X1_M.htm
da/rev_3/MUX_16X1_M.srd
da/rev_3/MUX_16X1_M.srm
da/rev_3/MUX_16X1_M.srr
da/rev_3/MUX_16X1_M.srs
da/rev_3/MUX_16X1_M.sxr
da/rev_3/MUX_16X1_M.tcl
da/rev_3/MUX_16X1_M.tlg
da/rev_3/MUX_16X1_M.vqm
da/rev_3/MUX_16X1_M.xrf
da/rev_3/MUX_16X1_M_cons.tcl
da/rev_3/MUX_16X1_M_rm.tcl
da/rev_3/Q_258_0_15_0_.mif
da/rev_3/Q_258_0_15_0_mif1.mif
da/rev_3/rpt_DA_top.areasrr
da/rev_3/rpt_DA_top_areasrr.htm
da/rev_3/syntmp/MUX_16X1_M.msg
da/rev_3/syntmp/MUX_16X1_M.plg
da/rev_3/syntmp/MUX_16X1_M_cons_ui.tcl
da/rev_3/syntmp/MUX_16X1_M_flink.htm
da/rev_3/syntmp/MUX_16X1_M_srr.htm
da/rev_3/syntmp/MUX_16X1_M_toc.htm
da/rev_3/verif/MUX_16X1_M.vif
da/shift_ram.v
da/sim/adder_mac.v
da/sim/ctrl_all.v
da/sim/dacase8_1.v
da/sim/dacase8_2.v
da/sim/DA_top.v
da/sim/DA_top_tb.v
da/sim/imp_in.txt
da/sim/MUX_16X1_M.v
da/sim/shift_ram.v
da/veryclean.bat
da/work/@d@a_top/verilog.asm
da/work/@d@a_top/_primary.dat
da/work/@d@a_top/_primary.vhd
da/work/@d@a_top_tb/verilog.asm
da/work/@d@a_top_tb/_primary.dat
da/work/@d@a_top_tb/_primary.vhd
da/work/@m@u@x_16@x1/verilog.asm
da/work/@m@u@x_16@x1/_primary.dat
da/work/@m@u@x_16@x1/_primary.vhd
da/work/adder_mac/verilog.asm
da/work/adder_mac/_primary.dat
da/work/adder_mac/_primary.vhd
da/work/ctrl_all/verilog.asm
da/work/ctrl_all/_primary.dat
da/work/ctrl_all/_primary.vhd
da/work/dacase8_1/verilog.asm
da/work/dacase8_1/_primary.dat
da/work/dacase8_1/_primary.vhd
da/work/dacase8_2/verilog.asm
da/work/dacase8_2/_primary.dat
da/work/dacase8_2/_primary.vhd
da/work/shift_ram/verilog.asm
da/work/shift_ram/_primary.dat
da/work/shift_ram/_primary.vhd
da/work/_info
da/rev_3/par_1
da/rev_3/syntmp
da/rev_3/verif
da/work/@d@a_top
da/work/@d@a_top_tb
da/work/@m@u@x_16@x1
da/work/adder_mac
da/work/ctrl_all
da/work/dacase8_1
da/work/dacase8_2
da/work/shift_ram
da/matlab_sim
da/rev_3
da/sim
da/work
da
da/ctrl_all.v
da/dacase8_1.v
da/dacase8_2.v
da/da_fir.prd
da/da_fir.prj
da/da_fir.qpf
da/DA_top.cr.mti
da/DA_top.mpf
da/DA_top.v
da/matlab_sim/fir_da.m
da/matlab_sim/fir_da_tb.m
da/matlab_sim/gencase.m
da/MUX_16X1_M.v
da/Q_258_0_15_0_.mif
da/Q_258_0_15_0_mif1.mif
da/readme.txt
da/rev_3/AutoConstraint_DA_top.sdc
da/rev_3/MUX_16X1_M.fse
da/rev_3/MUX_16X1_M.htm
da/rev_3/MUX_16X1_M.srd
da/rev_3/MUX_16X1_M.srm
da/rev_3/MUX_16X1_M.srr
da/rev_3/MUX_16X1_M.srs
da/rev_3/MUX_16X1_M.sxr
da/rev_3/MUX_16X1_M.tcl
da/rev_3/MUX_16X1_M.tlg
da/rev_3/MUX_16X1_M.vqm
da/rev_3/MUX_16X1_M.xrf
da/rev_3/MUX_16X1_M_cons.tcl
da/rev_3/MUX_16X1_M_rm.tcl
da/rev_3/Q_258_0_15_0_.mif
da/rev_3/Q_258_0_15_0_mif1.mif
da/rev_3/rpt_DA_top.areasrr
da/rev_3/rpt_DA_top_areasrr.htm
da/rev_3/syntmp/MUX_16X1_M.msg
da/rev_3/syntmp/MUX_16X1_M.plg
da/rev_3/syntmp/MUX_16X1_M_cons_ui.tcl
da/rev_3/syntmp/MUX_16X1_M_flink.htm
da/rev_3/syntmp/MUX_16X1_M_srr.htm
da/rev_3/syntmp/MUX_16X1_M_toc.htm
da/rev_3/verif/MUX_16X1_M.vif
da/shift_ram.v
da/sim/adder_mac.v
da/sim/ctrl_all.v
da/sim/dacase8_1.v
da/sim/dacase8_2.v
da/sim/DA_top.v
da/sim/DA_top_tb.v
da/sim/imp_in.txt
da/sim/MUX_16X1_M.v
da/sim/shift_ram.v
da/veryclean.bat
da/work/@d@a_top/verilog.asm
da/work/@d@a_top/_primary.dat
da/work/@d@a_top/_primary.vhd
da/work/@d@a_top_tb/verilog.asm
da/work/@d@a_top_tb/_primary.dat
da/work/@d@a_top_tb/_primary.vhd
da/work/@m@u@x_16@x1/verilog.asm
da/work/@m@u@x_16@x1/_primary.dat
da/work/@m@u@x_16@x1/_primary.vhd
da/work/adder_mac/verilog.asm
da/work/adder_mac/_primary.dat
da/work/adder_mac/_primary.vhd
da/work/ctrl_all/verilog.asm
da/work/ctrl_all/_primary.dat
da/work/ctrl_all/_primary.vhd
da/work/dacase8_1/verilog.asm
da/work/dacase8_1/_primary.dat
da/work/dacase8_1/_primary.vhd
da/work/dacase8_2/verilog.asm
da/work/dacase8_2/_primary.dat
da/work/dacase8_2/_primary.vhd
da/work/shift_ram/verilog.asm
da/work/shift_ram/_primary.dat
da/work/shift_ram/_primary.vhd
da/work/_info
da/rev_3/par_1
da/rev_3/syntmp
da/rev_3/verif
da/work/@d@a_top
da/work/@d@a_top_tb
da/work/@m@u@x_16@x1
da/work/adder_mac
da/work/ctrl_all
da/work/dacase8_1
da/work/dacase8_2
da/work/shift_ram
da/matlab_sim
da/rev_3
da/sim
da/work
da
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