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文件名称:or1200_wb_ram_gpio_pll

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  • 上传时间:
    2012-11-16
  • 文件大小:
    622.97kb
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Quartus ii项目,硬件平台为SOPC2000,能实现LED的各种显示控制及按键输入。包括硬件实现的Verilog及软件实现的C实现。SOPC系统的设计在Windows的quaruts ii 8.0上实现,软件部分在Ubuntu上实现。-Quartus ii project, the hardware platform for SOPC2000, to achieve a variety of LED display control and key input. Including Verilog hardware implementation and software implementation of the C implementation. SOPC system design in Windows, to achieve quaruts ii 8.0, software to achieve some of the Ubuntu.
相关搜索: or1200 qpf sopc20

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下载文件列表

or1200_wb_ram_gpio_pll/gpio/gpio_defines.v
or1200_wb_ram_gpio_pll/gpio/gpio_top.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_alu.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_amultp2_32x32.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_cfgr.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_cpu.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_ctrl.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_dc_fsm.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_dc_ram.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_dc_tag.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_dc_top.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_defines.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_defines.v.bak
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_dmmu_tlb.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_dmmu_top.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_dpram_256x32.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_dpram_32x32.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_du.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_except.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_freeze.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_genpc.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_gmultp2_32x32.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_ic_fsm.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_ic_ram.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_ic_tag.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_ic_top.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_if.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_immu_tlb.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_immu_top.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_iwb_biu.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_lsu.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_mem2reg.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_mult_mac.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_operandmuxes.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_pic.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_pm.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_qmem_top.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_reg2mem.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_rf.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_rfram_generic.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_sb.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_sb_fifo.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_spram_1024x32.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_spram_1024x32_bw.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_spram_1024x8.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_spram_128x32.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_spram_2048x32.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_spram_2048x32.v.bak
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_spram_2048x32_bw.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_spram_2048x8.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_spram_256x21.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_spram_32x24.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_spram_512x20.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_spram_64x14.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_spram_64x22.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_spram_64x24.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_sprs.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_top.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_tpram_32x32.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_tt.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_wbmux.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_wb_biu.v
or1200_wb_ram_gpio_pll/or1200-rel1/or1200_xcv_ram32x8d.v
or1200_wb_ram_gpio_pll/or1200-rel1/timescale.v
or1200_wb_ram_gpio_pll/or1200_sopc.asm.rpt
or1200_wb_ram_gpio_pll/or1200_sopc.done
or1200_wb_ram_gpio_pll/or1200_sopc.fit.rpt
or1200_wb_ram_gpio_pll/or1200_sopc.fit.smsg
or1200_wb_ram_gpio_pll/or1200_sopc.fit.summary
or1200_wb_ram_gpio_pll/or1200_sopc.flow.rpt
or1200_wb_ram_gpio_pll/or1200_sopc.map.rpt
or1200_wb_ram_gpio_pll/or1200_sopc.map.summary
or1200_wb_ram_gpio_pll/or1200_sopc.pin
or1200_wb_ram_gpio_pll/or1200_sopc.pof
or1200_wb_ram_gpio_pll/or1200_sopc.qpf
or1200_wb_ram_gpio_pll/or1200_sopc.qsf
or1200_wb_ram_gpio_pll/or1200_sopc.qws
or1200_wb_ram_gpio_pll/or1200_sopc.sof
or1200_wb_ram_gpio_pll/or1200_sopc.tan.rpt
or1200_wb_ram_gpio_pll/or1200_sopc.tan.summary
or1200_wb_ram_gpio_pll/or1200_sopc.v
or1200_wb_ram_gpio_pll/or1200_sopc.v.bak
or1200_wb_ram_gpio_pll/or1200_sys.v
or1200_wb_ram_gpio_pll/pll/cpu_pll.ppf
or1200_wb_ram_gpio_pll/pll/cpu_pll.qip
or1200_wb_ram_gpio_pll/pll/cpu_pll.v
or1200_wb_ram_gpio_pll/ram/ram.qip
or1200_wb_ram_gpio_pll/ram/ram.v
or1200_wb_ram_gpio_pll/ram/ram0_top.v
or1200_wb_ram_gpio_pll/ram0.mif
or1200_wb_ram_gpio_pll/Reset_Delay.v
or1200_wb_ram_gpio_pll/software/board.h
or1200_wb_ram_gpio_pll/software/gpio_or1200.c
or1200_wb_ram_gpio_pll/software/ihex2mif
or1200_wb_ram_gpio_pll/software/Makefile
or1200_wb_ram_gpio_pll/software/orsocdef.h
or1200_wb_ram_gpio_pll/software/ram.ld
or1200_wb_ram_gpio_pll/software/ram0.mif
or1200_wb_ram_gpio_pll/software/reset.S
or1200_wb_ram_gpio_pll/software/tools/ihex2mif.c
or1200_wb_ram_gpio_pll/software/tools/srec2mif.pl
or1200_wb_ram_gpio_pll/SOPC2000_pin.tcl
or1200_wb_ram_gpio_pll/wb_conmax/wb_conmax_arb.v
or1200_wb_ram_gpio_pll/wb_conmax/wb_conmax_defines.v
or1200_wb_ram_gpio_pll/wb_conmax/wb_conmax_master_if.v
or1200_wb_ram_gpio_pll/wb_conmax/wb_conmax_msel.v
or120

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