文件名称:UART
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- 上传时间:2012-11-16
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文件大小:748.17kb
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已下载:0次
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A sample that describe how to make wiring between modules using verilog ,it contain two stages of inverter of SW1 as input and LD7 as output
(系统自动生成,下载前可以参看下载内容)
下载文件列表
a/a.ise
a/a.ise_ISE_Backup
a/aa.v
a/aa_summary.html
a/genExpectedResults.cmd
a/isim/work/glbl/glbl.h
a/isim/work/glbl/mingw/glbl.obj
a/isim/work/hdllib.ref
a/isim/work/hdpdeps.ref
a/isim/work/test__bench/mingw/test__bench.obj
a/isim/work/test__bench/test__bench.h
a/isim/work/test__bench/xsimtest__bench.cpp
a/isim/work/uart/mingw/uart.obj
a/isim/work/uart/uart.h
a/isim/work/vlg27/test__bench.bin
a/isim/work/vlg2D/glbl.bin
a/isim/work/vlg48/uart.bin
a/isim/work/vlg5B/_u_a_r_t__bench.bin
a/isim/work/_u_a_r_t__bench/mingw/_u_a_r_t__bench.obj
a/isim/work/_u_a_r_t__bench/xsim_u_a_r_t__bench.cpp
a/isim/work/_u_a_r_t__bench/_u_a_r_t__bench.h
a/isim.cmd
a/isim.hdlsourcefiles
a/isim.log
a/isim.tmp_save/_1
a/isimwavedata.xwv
a/prjname.lso
a/results.txt
a/test_bench.ano
a/test_bench.ant
a/test_bench.jhd
a/test_bench.tbw
a/test_bench.tfw
a/test_bench.xwv
a/test_bench.xwv_bak
a/test_bench_beh.prj
a/test_bench_bencher.prj
a/test_bench_gen.prj
a/test_bench_isim_beh.exe
a/test_bench_tbxr.exe
a/tmpRTVStore.xwv
a/uart.bgn
a/uart.bit
a/uart.bld
a/uart.cmd_log
a/uart.drc
a/uart.lfp
a/uart.lso
a/uart.ncd
a/uart.ngc
a/uart.ngd
a/uart.ngr
a/uart.pad
a/uart.par
a/uart.pcf
a/uart.prj
a/uart.stx
a/uart.syr
a/uart.twr
a/uart.twx
a/uart.ucf
a/uart.unroutes
a/uart.ut
a/uart.xpi
a/uart.xst
a/UART_bench.ano
a/UART_bench.ant
a/UART_bench.jhd
a/UART_bench.tbw
a/UART_bench.tfw
a/UART_bench.xwv
a/UART_bench.xwv_bak
a/UART_bench_bencher.prj
a/UART_bench_gen.prj
a/UART_bench_tbxr.exe
a/uart_last_par.ncd
a/uart_map.mrp
a/uart_map.ncd
a/uart_map.ngm
a/uart_pad.csv
a/uart_pad.txt
a/uart_summary.html
a/uart_vhdl.prj
a/xilinxsim.ini
a/xst/work/hdllib.ref
a/xst/work/vlg48/uart.bin
a/_impact.cmd
a/_impact.log
a/_ngo/netlist.lst
a/_pace.ucf
a/_xmsgs/bitgen.xmsgs
a/_xmsgs/fuse.xmsgs
a/_xmsgs/map.xmsgs
a/_xmsgs/ngdbuild.xmsgs
a/_xmsgs/par.xmsgs
a/_xmsgs/trce.xmsgs
a/_xmsgs/xst.xmsgs
a/xst/dump.xst/uart.prj/ngx/notopt
a/xst/dump.xst/uart.prj/ngx/opt
a/isim/work/glbl/mingw
a/isim/work/test__bench/mingw
a/isim/work/uart/mingw
a/isim/work/_u_a_r_t__bench/mingw
a/xst/dump.xst/uart.prj/ngx
a/isim/work/glbl
a/isim/work/test__bench
a/isim/work/uart
a/isim/work/vlg27
a/isim/work/vlg2D
a/isim/work/vlg48
a/isim/work/vlg5B
a/isim/work/_u_a_r_t__bench
a/xst/dump.xst/uart.prj
a/xst/work/vlg48
a/isim/work
a/xst/dump.xst
a/xst/projnav.tmp
a/xst/work
a/isim
a/isim.tmp_save
a/xst
a/_ngo
a/_xmsgs
a
a/a.ise_ISE_Backup
a/aa.v
a/aa_summary.html
a/genExpectedResults.cmd
a/isim/work/glbl/glbl.h
a/isim/work/glbl/mingw/glbl.obj
a/isim/work/hdllib.ref
a/isim/work/hdpdeps.ref
a/isim/work/test__bench/mingw/test__bench.obj
a/isim/work/test__bench/test__bench.h
a/isim/work/test__bench/xsimtest__bench.cpp
a/isim/work/uart/mingw/uart.obj
a/isim/work/uart/uart.h
a/isim/work/vlg27/test__bench.bin
a/isim/work/vlg2D/glbl.bin
a/isim/work/vlg48/uart.bin
a/isim/work/vlg5B/_u_a_r_t__bench.bin
a/isim/work/_u_a_r_t__bench/mingw/_u_a_r_t__bench.obj
a/isim/work/_u_a_r_t__bench/xsim_u_a_r_t__bench.cpp
a/isim/work/_u_a_r_t__bench/_u_a_r_t__bench.h
a/isim.cmd
a/isim.hdlsourcefiles
a/isim.log
a/isim.tmp_save/_1
a/isimwavedata.xwv
a/prjname.lso
a/results.txt
a/test_bench.ano
a/test_bench.ant
a/test_bench.jhd
a/test_bench.tbw
a/test_bench.tfw
a/test_bench.xwv
a/test_bench.xwv_bak
a/test_bench_beh.prj
a/test_bench_bencher.prj
a/test_bench_gen.prj
a/test_bench_isim_beh.exe
a/test_bench_tbxr.exe
a/tmpRTVStore.xwv
a/uart.bgn
a/uart.bit
a/uart.bld
a/uart.cmd_log
a/uart.drc
a/uart.lfp
a/uart.lso
a/uart.ncd
a/uart.ngc
a/uart.ngd
a/uart.ngr
a/uart.pad
a/uart.par
a/uart.pcf
a/uart.prj
a/uart.stx
a/uart.syr
a/uart.twr
a/uart.twx
a/uart.ucf
a/uart.unroutes
a/uart.ut
a/uart.xpi
a/uart.xst
a/UART_bench.ano
a/UART_bench.ant
a/UART_bench.jhd
a/UART_bench.tbw
a/UART_bench.tfw
a/UART_bench.xwv
a/UART_bench.xwv_bak
a/UART_bench_bencher.prj
a/UART_bench_gen.prj
a/UART_bench_tbxr.exe
a/uart_last_par.ncd
a/uart_map.mrp
a/uart_map.ncd
a/uart_map.ngm
a/uart_pad.csv
a/uart_pad.txt
a/uart_summary.html
a/uart_vhdl.prj
a/xilinxsim.ini
a/xst/work/hdllib.ref
a/xst/work/vlg48/uart.bin
a/_impact.cmd
a/_impact.log
a/_ngo/netlist.lst
a/_pace.ucf
a/_xmsgs/bitgen.xmsgs
a/_xmsgs/fuse.xmsgs
a/_xmsgs/map.xmsgs
a/_xmsgs/ngdbuild.xmsgs
a/_xmsgs/par.xmsgs
a/_xmsgs/trce.xmsgs
a/_xmsgs/xst.xmsgs
a/xst/dump.xst/uart.prj/ngx/notopt
a/xst/dump.xst/uart.prj/ngx/opt
a/isim/work/glbl/mingw
a/isim/work/test__bench/mingw
a/isim/work/uart/mingw
a/isim/work/_u_a_r_t__bench/mingw
a/xst/dump.xst/uart.prj/ngx
a/isim/work/glbl
a/isim/work/test__bench
a/isim/work/uart
a/isim/work/vlg27
a/isim/work/vlg2D
a/isim/work/vlg48
a/isim/work/vlg5B
a/isim/work/_u_a_r_t__bench
a/xst/dump.xst/uart.prj
a/xst/work/vlg48
a/isim/work
a/xst/dump.xst
a/xst/projnav.tmp
a/xst/work
a/isim
a/isim.tmp_save
a/xst
a/_ngo
a/_xmsgs
a
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