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文件名称:CPU

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    7.97mb
  • 已下载：
    0次
  • 提 供 者：
    张***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于32位MIPS流水线CPU，由自己独立完成，-Pipelined 32-bit MIPS-based CPU, by themselves independently,
(系统自动生成,下载前可以参看下载内容)

下载文件列表

CPU/
CPU/CPU.asm.rpt
CPU/CPU.done
CPU/CPU.eda.rpt
CPU/CPU.fit.rpt
CPU/CPU.fit.smsg
CPU/CPU.fit.summary
CPU/CPU.flow.rpt
CPU/CPU.map.rpt
CPU/CPU.map.smsg
CPU/CPU.map.summary
CPU/CPU.pin
CPU/CPU.pof
CPU/CPU.qpf
CPU/CPU.qsf
CPU/CPU.sof
CPU/CPU.tan.rpt
CPU/CPU.tan.summary
CPU/CPU_nativelink_simulation.rpt
CPU/db/
CPU/db/CPU.(0).cnf.cdb
CPU/db/CPU.(0).cnf.hdb
CPU/db/CPU.(1).cnf.cdb
CPU/db/CPU.(1).cnf.hdb
CPU/db/CPU.(2).cnf.cdb
CPU/db/CPU.(2).cnf.hdb
CPU/db/CPU.(3).cnf.cdb
CPU/db/CPU.(3).cnf.hdb
CPU/db/CPU.(4).cnf.cdb
CPU/db/CPU.(4).cnf.hdb
CPU/db/CPU.(5).cnf.cdb
CPU/db/CPU.(5).cnf.hdb
CPU/db/CPU.(6).cnf.cdb
CPU/db/CPU.(6).cnf.hdb
CPU/db/CPU.(7).cnf.cdb
CPU/db/CPU.(7).cnf.hdb
CPU/db/CPU.(8).cnf.cdb
CPU/db/CPU.(8).cnf.hdb
CPU/db/CPU.ae.hdb
CPU/db/CPU.asm.qmsg
CPU/db/CPU.cbx.xml
CPU/db/CPU.cmp.bpm
CPU/db/CPU.cmp.cdb
CPU/db/CPU.cmp.ecobp
CPU/db/CPU.cmp.hdb
CPU/db/CPU.cmp.kpt
CPU/db/CPU.cmp.logdb
CPU/db/CPU.cmp.rdb
CPU/db/CPU.cmp.tdb
CPU/db/CPU.cmp0.ddb
CPU/db/CPU.cmp_merge.kpt
CPU/db/CPU.db_info
CPU/db/CPU.eco.cdb
CPU/db/CPU.eda.qmsg
CPU/db/CPU.fit.qmsg
CPU/db/CPU.hier_info
CPU/db/CPU.hif
CPU/db/CPU.lpc.html
CPU/db/CPU.lpc.rdb
CPU/db/CPU.lpc.txt
CPU/db/CPU.map.bpm
CPU/db/CPU.map.cdb
CPU/db/CPU.map.ecobp
CPU/db/CPU.map.hdb
CPU/db/CPU.map.kpt
CPU/db/CPU.map.logdb
CPU/db/CPU.map.qmsg
CPU/db/CPU.map_bb.cdb
CPU/db/CPU.map_bb.hdb
CPU/db/CPU.map_bb.logdb
CPU/db/CPU.pre_map.cdb
CPU/db/CPU.pre_map.hdb
CPU/db/CPU.rpp.qmsg
CPU/db/CPU.rtlv.hdb
CPU/db/CPU.rtlv_sg.cdb
CPU/db/CPU.rtlv_sg_swap.cdb
CPU/db/CPU.sgate.rvd
CPU/db/CPU.sgate_sm.rvd
CPU/db/CPU.sgdiff.cdb
CPU/db/CPU.sgdiff.hdb
CPU/db/CPU.sld_design_entry.sci
CPU/db/CPU.sld_design_entry_dsc.sci
CPU/db/CPU.smp_dump.txt
CPU/db/CPU.syn_hier_info
CPU/db/CPU.tan.qmsg
CPU/db/CPU.tis_db_list.ddb
CPU/db/CPU_global_asgn_op.abo
CPU/db/prev_cmp_CPU.asm.qmsg
CPU/db/prev_cmp_CPU.eda.qmsg
CPU/db/prev_cmp_CPU.fit.qmsg
CPU/db/prev_cmp_CPU.map.qmsg
CPU/db/prev_cmp_CPU.qmsg
CPU/db/prev_cmp_CPU.tan.qmsg
CPU/incremental_db/
CPU/incremental_db/compiled_partitions/
CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.atm
CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.dfp
CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.hdbx
CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.kpt
CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.logdb
CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.rcf
CPU/incremental_db/compiled_partitions/CPU.root_partition.map.atm
CPU/incremental_db/compiled_partitions/CPU.root_partition.map.dpi
CPU/incremental_db/compiled_partitions/CPU.root_partition.map.hdbx
CPU/incremental_db/compiled_partitions/CPU.root_partition.map.kpt
CPU/incremental_db/README
CPU/simulation/
CPU/simulation/modelsim/
CPU/simulation/modelsim/CPU.sft
CPU/simulation/modelsim/CPU.vo
CPU/simulation/modelsim/CPU_modelsim.xrf
CPU/simulation/modelsim/CPU_run_msim_gate_verilog.do
CPU/simulation/modelsim/CPU_run_msim_gate_verilog.do.bak
CPU/simulation/modelsim/CPU_run_msim_gate_verilog.do.bak1
CPU/simulation/modelsim/CPU_run_msim_gate_verilog.do.bak2
CPU/simulation/modelsim/CPU_run_msim_gate_verilog.do.bak3
CPU/simulation/modelsim/CPU_run_msim_gate_verilog.do.bak4
CPU/simulation/modelsim/CPU_run_msim_rtl_verilog.do
CPU/simulation/modelsim/CPU_run_msim_rtl_verilog.do.bak
CPU/simulation/modelsim/CPU_v.sdo
CPU/simulation/modelsim/CPU_v.sdo_typ.csd
CPU/simulation/modelsim/gate_work/
CPU/simulation/modelsim/gate_work/addr_decode/
CPU/simulation/modelsim/gate_work/addr_decode/verilog.asm
CPU/simulation/modelsim/gate_work/addr_decode/verilog.rw
CPU/simulation/modelsim/gate_work/addr_decode/_primary.dat
CPU/simulation/modelsim/gate_work/addr_decode/_primary.dbs
CPU/simulation/modelsim/gate_work/addr_decode/_primary.vhd
CPU/simulation/modelsim/gate_work/cpu/
CPU/simulation/modelsim/gate_work/cpu/verilog.asm
CPU/simulation/modelsim/gate_work/cpu/verilog.rw
CPU/simulation/modelsim/gate_work/cpu/_primary.dat
CPU/simulation/modelsim/gate_work/cpu/_primary.dbs
CPU/simulation/modelsim/gate_work/cpu/_primary.vhd
CPU/simulation/modelsim/gate_work/cpu_tb/
CPU/simulation/modelsim/gate_work/cpu_tb/verilog.asm
CPU/simulation/modelsim/gate_work/cpu_tb/verilog.rw
CPU/simulation/modelsim/gate_work/cpu_tb/_primary.dat
CPU/simulation/modelsim/gate_work/cpu_tb/_primary.dbs
CPU/simulation/modelsim/gate_work/cpu_tb/_primary.vhd
CPU/simulation/modelsim/gate_work/ram/
CPU/simulation/modelsim/gate_work/ram/verilog.asm
CPU/simulation/modelsim/gate_work/ram/verilog.rw
CPU/simulation/modelsim/gate_work/ram/_primary.dat
CPU/simulation/modelsim/gate_work/ram/_primary.dbs
CPU/simulation/modelsim/gate_work/ram/_primary.vhd
CPU/simulation/modelsim/gate_work/rom/
CPU/simulation/modelsim/gate_work/rom/verilog.asm
CPU/simulation/modelsim/gate_work/rom/verilog.rw
CPU/simulation/modelsim/gate_work/rom/_primary.dat
CPU/simulation/modelsim/gate_work/rom/_primary.dbs
CPU/simulation/modelsim/gate_work/rom/_primary.vhd
CPU/simulation/modelsim/gate_work/_info
CPU/simulation/modelsim/gate_work/_temp/
CPU/simulation/modelsim/gate_work/_vmake
CPU/simulation/modelsim/modelsim.ini
CPU/simulation/modelsim/msim_tran

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