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文件名称:div_n_0_5

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    770.43kb
  • 已下载：
    0次
  • 提 供 者：
    li***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

使用verilog实现任意奇数n+0.5分频，使用ise11.1和modelsim se6.5仿真测试-Using an arbitrary odd number n+0.5 verilog divide, the use of simulation testing ise11.1 and modelsim se6.5
(系统自动生成,下载前可以参看下载内容)

下载文件列表

div_n_0_5/.cxl.mti_se.version
div_n_0_5/.lso
div_n_0_5/compxlib.log
div_n_0_5/div_n_0_5.cmd_log
div_n_0_5/div_n_0_5.gise
div_n_0_5/div_n_0_5.ise
div_n_0_5/div_n_0_5.lso
div_n_0_5/div_n_0_5.ngc
div_n_0_5/div_n_0_5.ngr
div_n_0_5/div_n_0_5.ntrc_log
div_n_0_5/div_n_0_5.prj
div_n_0_5/div_n_0_5.stx
div_n_0_5/div_n_0_5.syr
div_n_0_5/div_n_0_5.udo
div_n_0_5/div_n_0_5.v
div_n_0_5/div_n_0_5.xise
div_n_0_5/div_n_0_5.xst
div_n_0_5/div_n_0_5_summary.html
div_n_0_5/div_n_0_5_wave.fdo
div_n_0_5/div_n_0_5_xdb/cst.xbcd
div_n_0_5/div_n_0_5_xdb/tmp/ise/version
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/__stored_object_table__
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/CViewSelector
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/CViewSelector_StrTbl
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/File-SynthesisOnly
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/File-SynthesisOnly_StrTbl
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Library-SynthesisOnly
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Library-SynthesisOnly_StrTbl
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-BehavioralSim-
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-BehavioralSim-DESUT_VERILOG
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-BehavioralSim-DESUT_VERILOG_StrTbl
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-BehavioralSim-_StrTbl
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-DESUT_VERILOG
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-DESUT_VERILOG_StrTbl
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-_StrTbl
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Source-BehavioralSim-AutoCompile
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Source-BehavioralSim-AutoCompile_StrTbl
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Source-SynthesisOnly-AutoCompile
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Source-SynthesisOnly-AutoCompile_StrTbl
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Current-Module
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Current-Module_StrTbl
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-div_n_0_5
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-div_n_0_5_StrTbl
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-div_odd
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-div_odd_StrTbl
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-DataFactory-Default
div_n_0_5/div_n_0_5_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/Autonym/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/bitinit/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/common/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/fuse/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/idem/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/libgen/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/map/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/netgen/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/par/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/platgen/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/ProjectNavigator11/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/ProjectNavigatorGui/regkeys
div_n_0_5/div_n_0_5_xdb/tmp/ise/__REGISTRY__/runner/regkeys
div_n_0_5/div_n_0_5_xdb/tm

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