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文件名称:VGA

  • 所属分类:
  • 标签属性:
  • 上传时间:
    2012-11-16
  • 文件大小:
    567.79kb
  • 已下载:
    0次
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  • 相关连接:
  • 下载说明:
    别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容来自于网络,使用问题请自行百度

VERILOG编写的VGA实验例程,包括整个工程,可以直接使用-VERILOG VGA written test routines, including the whole project, can be used directly
相关搜索: VGA VERILOG

(系统自动生成,下载前可以参看下载内容)

下载文件列表

VGA实验/Project/VGA/constraint/vgatest.pdc
VGA实验/Project/VGA/constraint/vgatest_1.pdc
VGA实验/Project/VGA/designer/impl1/designer.log
VGA实验/Project/VGA/designer/impl1/designer_genhdl.log
VGA实验/Project/VGA/designer/impl1/vgatest.adb
VGA实验/Project/VGA/designer/impl1/vgatest.dtf/verify.log
VGA实验/Project/VGA/designer/impl1/vgatest.ide_des
VGA实验/Project/VGA/designer/impl1/vgatest.pdb
VGA实验/Project/VGA/designer/impl1/vgatest.pdb.depends
VGA实验/Project/VGA/designer/impl1/vgatest.tcl
VGA实验/Project/VGA/designer/impl1/vgatest_ba.sdf
VGA实验/Project/VGA/designer/impl1/vgatest_ba.v
VGA实验/Project/VGA/designer/impl1/vgatest_fp/$$FlashPro_02165.L$$
VGA实验/Project/VGA/designer/impl1/vgatest_fp/$$FlashPro_FPBBALTLPT1.L$$
VGA实验/Project/VGA/designer/impl1/vgatest_fp/projectData/vgatest.pdb
VGA实验/Project/VGA/designer/impl1/vgatest_fp/vgatest.log
VGA实验/Project/VGA/designer/impl1/vgatest_fp/vgatest.pro
VGA实验/Project/VGA/hdl/hdlsynchk.tcl
VGA实验/Project/VGA/hdl/vgatest.v
VGA实验/Project/VGA/simulation/meminit.dat
VGA实验/Project/VGA/simulation/modelsim.ini
VGA实验/Project/VGA/simulation/modelsim.ini.sav
VGA实验/Project/VGA/smartgen/smartgen.aws
VGA实验/Project/VGA/synthesis/.recordref
VGA实验/Project/VGA/synthesis/stdout.log
VGA实验/Project/VGA/synthesis/syntmp/sap.log
VGA实验/Project/VGA/synthesis/syntmp/vgatest.msg
VGA实验/Project/VGA/synthesis/syntmp/vgatest.plg
VGA实验/Project/VGA/synthesis/syntmp/vgatest_flink.htm
VGA实验/Project/VGA/synthesis/syntmp/vgatest_srr.htm
VGA实验/Project/VGA/synthesis/syntmp/vgatest_toc.htm
VGA实验/Project/VGA/synthesis/traplog.tlg
VGA实验/Project/VGA/synthesis/vgatest.areasrr
VGA实验/Project/VGA/synthesis/vgatest.edn
VGA实验/Project/VGA/synthesis/vgatest.fse
VGA实验/Project/VGA/synthesis/vgatest.htm
VGA实验/Project/VGA/synthesis/vgatest.map
VGA实验/Project/VGA/synthesis/vgatest.sap
VGA实验/Project/VGA/synthesis/vgatest.sdf
VGA实验/Project/VGA/synthesis/vgatest.srd
VGA实验/Project/VGA/synthesis/vgatest.srm
VGA实验/Project/VGA/synthesis/vgatest.srr
VGA实验/Project/VGA/synthesis/vgatest.srs
VGA实验/Project/VGA/synthesis/vgatest.tlg
VGA实验/Project/VGA/synthesis/vgatest_drc.rpt
VGA实验/Project/VGA/synthesis/vgatest_sdc.sdc
VGA实验/Project/VGA/synthesis/vgatest_syn.prd
VGA实验/Project/VGA/synthesis/vgatest_syn.prj
VGA实验/Project/VGA/VGA.prj
VGA实验/Project/VGA/viewdraw/vf/project.lst
VGA实验/Project/VGA/viewdraw/viewdraw.ini
VGA实验/Source/vgatest.v
VGA实验/Project/VGA/designer/impl1/vgatest_fp/projectData
VGA实验/Project/VGA/designer/impl1/simulation
VGA实验/Project/VGA/designer/impl1/vgatest.dtf
VGA实验/Project/VGA/designer/impl1/vgatest_fp
VGA实验/Project/VGA/designer/impl1
VGA实验/Project/VGA/synthesis/syntmp
VGA实验/Project/VGA/viewdraw/sch
VGA实验/Project/VGA/viewdraw/sym
VGA实验/Project/VGA/viewdraw/vf
VGA实验/Project/VGA/viewdraw/wir
VGA实验/Project/VGA/component
VGA实验/Project/VGA/constraint
VGA实验/Project/VGA/coreconsole
VGA实验/Project/VGA/designer
VGA实验/Project/VGA/hdl
VGA实验/Project/VGA/phy_synthesis
VGA实验/Project/VGA/simulation
VGA实验/Project/VGA/smartgen
VGA实验/Project/VGA/stimulus
VGA实验/Project/VGA/synthesis
VGA实验/Project/VGA/viewdraw
VGA实验/Project/VGA
VGA实验/Project
VGA实验/Source
VGA实验

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