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文件名称:ADCODE

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    10.67mb
  • 已下载：
    0次
  • 提 供 者：
    龙**
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

用FPGA控制双ADC0809读写，用于双AD热备控制，用verilog实现-FPGA control with dual ADC0809 read and write, hot standby control for double AD, with verilog implementation
(系统自动生成,下载前可以参看下载内容)

下载文件列表

SPICODE/
SPICODE/code/
SPICODE/quartus/
SPICODE/quartus/adselfcheck.v
SPICODE/quartus/adselfcheck.v.bak
SPICODE/quartus/ad_cycle.v
SPICODE/quartus/ad_cycle.v.bak
SPICODE/quartus/ad_process.v.bak
SPICODE/quartus/ad_process0.v
SPICODE/quartus/ad_process0.v.bak
SPICODE/quartus/ad_process1.v
SPICODE/quartus/ad_process1.v.bak
SPICODE/quartus/ad_top.v
SPICODE/quartus/ad_top.v.bak
SPICODE/quartus/db/
SPICODE/quartus/db/logic_util_heursitic.dat
SPICODE/quartus/db/prev_cmp_SPI_Master.asm.qmsg
SPICODE/quartus/db/prev_cmp_SPI_Master.eda.qmsg
SPICODE/quartus/db/prev_cmp_SPI_Master.fit.qmsg
SPICODE/quartus/db/prev_cmp_SPI_Master.map.qmsg
SPICODE/quartus/db/prev_cmp_SPI_Master.qmsg
SPICODE/quartus/db/prev_cmp_SPI_Master.tan.qmsg
SPICODE/quartus/db/SPI_Master.(0).cnf.cdb
SPICODE/quartus/db/SPI_Master.(0).cnf.hdb
SPICODE/quartus/db/SPI_Master.(1).cnf.cdb
SPICODE/quartus/db/SPI_Master.(1).cnf.hdb
SPICODE/quartus/db/SPI_Master.(2).cnf.cdb
SPICODE/quartus/db/SPI_Master.(2).cnf.hdb
SPICODE/quartus/db/SPI_Master.(3).cnf.cdb
SPICODE/quartus/db/SPI_Master.(3).cnf.hdb
SPICODE/quartus/db/SPI_Master.(4).cnf.cdb
SPICODE/quartus/db/SPI_Master.(4).cnf.hdb
SPICODE/quartus/db/SPI_Master.asm.qmsg
SPICODE/quartus/db/SPI_Master.asm.rdb
SPICODE/quartus/db/SPI_Master.asm_labs.ddb
SPICODE/quartus/db/SPI_Master.cbx.xml
SPICODE/quartus/db/SPI_Master.cmp.cdb
SPICODE/quartus/db/SPI_Master.cmp.hdb
SPICODE/quartus/db/SPI_Master.cmp.kpt
SPICODE/quartus/db/SPI_Master.cmp.logdb
SPICODE/quartus/db/SPI_Master.cmp.rdb
SPICODE/quartus/db/SPI_Master.cmp.tdb
SPICODE/quartus/db/SPI_Master.cmp0.ddb
SPICODE/quartus/db/SPI_Master.db_info
SPICODE/quartus/db/SPI_Master.eco.cdb
SPICODE/quartus/db/SPI_Master.eda.qmsg
SPICODE/quartus/db/SPI_Master.fit.qmsg
SPICODE/quartus/db/SPI_Master.hier_info
SPICODE/quartus/db/SPI_Master.hif
SPICODE/quartus/db/SPI_Master.lpc.html
SPICODE/quartus/db/SPI_Master.lpc.rdb
SPICODE/quartus/db/SPI_Master.lpc.txt
SPICODE/quartus/db/SPI_Master.map.cdb
SPICODE/quartus/db/SPI_Master.map.hdb
SPICODE/quartus/db/SPI_Master.map.logdb
SPICODE/quartus/db/SPI_Master.map.qmsg
SPICODE/quartus/db/SPI_Master.pre_map.cdb
SPICODE/quartus/db/SPI_Master.pre_map.hdb
SPICODE/quartus/db/SPI_Master.rpp.qmsg
SPICODE/quartus/db/SPI_Master.rtlv.hdb
SPICODE/quartus/db/SPI_Master.rtlv_sg.cdb
SPICODE/quartus/db/SPI_Master.rtlv_sg_swap.cdb
SPICODE/quartus/db/SPI_Master.sgate.rvd
SPICODE/quartus/db/SPI_Master.sgate_sm.rvd
SPICODE/quartus/db/SPI_Master.sgdiff.cdb
SPICODE/quartus/db/SPI_Master.sgdiff.hdb
SPICODE/quartus/db/SPI_Master.sld_design_entry.sci
SPICODE/quartus/db/SPI_Master.sld_design_entry_dsc.sci
SPICODE/quartus/db/SPI_Master.smart_action.txt
SPICODE/quartus/db/SPI_Master.smp_dump.txt
SPICODE/quartus/db/SPI_Master.syn_hier_info
SPICODE/quartus/db/SPI_Master.tan.qmsg
SPICODE/quartus/db/SPI_Master.tis_db_list.ddb
SPICODE/quartus/db/SPI_Master.tmw_info
SPICODE/quartus/incremental_db/
SPICODE/quartus/incremental_db/compiled_partitions/
SPICODE/quartus/incremental_db/compiled_partitions/SPI_Master.root_partition.map.kpt
SPICODE/quartus/incremental_db/README
SPICODE/quartus/simulation/
SPICODE/quartus/simulation/modelsim/
SPICODE/quartus/simulation/modelsim/modelsim.ini
SPICODE/quartus/simulation/modelsim/msim_transcript
SPICODE/quartus/simulation/modelsim/rtl_work/
SPICODE/quartus/simulation/modelsim/rtl_work/adselfcheck/
SPICODE/quartus/simulation/modelsim/rtl_work/adselfcheck/verilog.prw
SPICODE/quartus/simulation/modelsim/rtl_work/adselfcheck/verilog.psm
SPICODE/quartus/simulation/modelsim/rtl_work/adselfcheck/_primary.dat
SPICODE/quartus/simulation/modelsim/rtl_work/adselfcheck/_primary.dbs
SPICODE/quartus/simulation/modelsim/rtl_work/adselfcheck/_primary.vhd
SPICODE/quartus/simulation/modelsim/rtl_work/ad_cycle/
SPICODE/quartus/simulation/modelsim/rtl_work/ad_cycle/verilog.prw
SPICODE/quartus/simulation/modelsim/rtl_work/ad_cycle/verilog.psm
SPICODE/quartus/simulation/modelsim/rtl_work/ad_cycle/_primary.dat
SPICODE/quartus/simulation/modelsim/rtl_work/ad_cycle/_primary.dbs
SPICODE/quartus/simulation/modelsim/rtl_work/ad_cycle/_primary.vhd
SPICODE/quartus/simulation/modelsim/rtl_work/ad_process0/
SPICODE/quartus/simulation/modelsim/rtl_work/ad_process0/verilog.prw
SPICODE/quartus/simulation/modelsim/rtl_work/ad_process0/verilog.psm
SPICODE/quartus/simulation/modelsim/rtl_work/ad_process0/_primary.dat
SPICODE/quartus/simulation/modelsim/rtl_work/ad_process0/_primary.dbs
SPICODE/quartus/simulation/modelsim/rtl_work/ad_process0/_primary.vhd
SPICODE/quartus/simulation/modelsim/rtl_work/ad_process1/
SPICODE/quartus/simulation/modelsim/rtl_work/ad_process1/verilog.prw
SPICODE/quartus/simulation/modelsim/rtl_work/ad_process1/verilog.psm
SPICODE/quartus/simulation/modelsim/rtl_work/ad_process1/_primary.dat
SPICODE/quartus/simulation/modelsim/rtl_work/ad_process1/_primary.dbs
SPICODE/quartus/simulation/modelsim/rtl_work/ad_process1/_primary.vhd
SPICODE/quartus/simulation/modelsim/rtl_work/ad_test/
SPICODE/quartus/simulation/modelsim/rtl_work/ad_test/verilog.prw
SPICODE/quartus/simulation/modelsim/rtl_work/ad_test/verilog.psm
SPICODE/quartus/simulation/modelsim/rtl_work/ad_test/_primary

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