CDN加速镜像 | 设为首页 | 加入收藏夹
登陆 | 会员注册
当前位置： 首页 资源下载 源码下载 嵌入式/单片机编程 VHDL编程
收藏

文件名称:LIP2131CORE_dram_controller

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    7.76mb
  • 已下载：
    0次
  • 提 供 者：
    j***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

LIP2131 CORE Verilog DRAM Controller
(系统自动生成,下载前可以参看下载内容)

下载文件列表

bench/main.v
bench/sim_nc/architecture.v
bench/sim_nc/run
bench/sim_nc/sim.v
bench/sim_nc/CVS/Entries
bench/sim_nc/CVS/Repository
bench/sim_nc/CVS/Root
bench/sim_mc_Tek-5.2/run
bench/sim_mc_Tek-5.2/sim.v
bench/sim_mc_Tek-5.2/output/pack/README
bench/sim_mc_Tek-5.2/output/pack/CVS/Entries
bench/sim_mc_Tek-5.2/output/pack/CVS/Repository
bench/sim_mc_Tek-5.2/output/pack/CVS/Root
bench/sim_mc_Tek-5.2/output/normal/README
bench/sim_mc_Tek-5.2/output/normal/CVS/Entries
bench/sim_mc_Tek-5.2/output/normal/CVS/Repository
bench/sim_mc_Tek-5.2/output/normal/CVS/Root
bench/sim_mc_Tek-5.2/output/downsample/README
bench/sim_mc_Tek-5.2/output/downsample/CVS/Entries
bench/sim_mc_Tek-5.2/output/downsample/CVS/Repository
bench/sim_mc_Tek-5.2/output/downsample/CVS/Root
bench/sim_mc_Tek-5.2/output/CVS/Entries
bench/sim_mc_Tek-5.2/output/CVS/Repository
bench/sim_mc_Tek-5.2/output/CVS/Root
bench/sim_mc_Tek-5.2/debug_utils/diffall
bench/sim_mc_Tek-5.2/debug_utils/generate_ppm
bench/sim_mc_Tek-5.2/debug_utils/showRam.awk
bench/sim_mc_Tek-5.2/debug_utils/Tek-5.2_disp.stat
bench/sim_mc_Tek-5.2/debug_utils/CVS/Entries
bench/sim_mc_Tek-5.2/debug_utils/CVS/Repository
bench/sim_mc_Tek-5.2/debug_utils/CVS/Root
bench/sim_mc_Tek-5.2/CVS/Entries
bench/sim_mc_Tek-5.2/CVS/Repository
bench/sim_mc_Tek-5.2/CVS/Root
bench/sim_mc_tcela-17/run
bench/sim_mc_tcela-17/sim.v
bench/sim_mc_tcela-17/output/pack/README
bench/sim_mc_tcela-17/output/pack/CVS/Entries
bench/sim_mc_tcela-17/output/pack/CVS/Repository
bench/sim_mc_tcela-17/output/pack/CVS/Root
bench/sim_mc_tcela-17/output/normal/README
bench/sim_mc_tcela-17/output/normal/CVS/Entries
bench/sim_mc_tcela-17/output/normal/CVS/Repository
bench/sim_mc_tcela-17/output/normal/CVS/Root
bench/sim_mc_tcela-17/output/downsample/README
bench/sim_mc_tcela-17/output/downsample/CVS/Entries
bench/sim_mc_tcela-17/output/downsample/CVS/Repository
bench/sim_mc_tcela-17/output/downsample/CVS/Root
bench/sim_mc_tcela-17/output/CVS/Entries
bench/sim_mc_tcela-17/output/CVS/Repository
bench/sim_mc_tcela-17/output/CVS/Root
bench/sim_mc_tcela-17/debug_utils/diffall
bench/sim_mc_tcela-17/debug_utils/generate_ppm
bench/sim_mc_tcela-17/debug_utils/showRam.awk
bench/sim_mc_tcela-17/debug_utils/tcela-17_disp.stat
bench/sim_mc_tcela-17/debug_utils/CVS/Entries
bench/sim_mc_tcela-17/debug_utils/CVS/Repository
bench/sim_mc_tcela-17/debug_utils/CVS/Root
bench/sim_mc_tcela-17/CVS/Entries
bench/sim_mc_tcela-17/CVS/Repository
bench/sim_mc_tcela-17/CVS/Root
bench/sim_mc_sony-ct3/run
bench/sim_mc_sony-ct3/sim.v
bench/sim_mc_sony-ct3/output/pack/README
bench/sim_mc_sony-ct3/output/pack/CVS/Entries
bench/sim_mc_sony-ct3/output/pack/CVS/Repository
bench/sim_mc_sony-ct3/output/pack/CVS/Root
bench/sim_mc_sony-ct3/output/normal/README
bench/sim_mc_sony-ct3/output/normal/CVS/Entries
bench/sim_mc_sony-ct3/output/normal/CVS/Repository
bench/sim_mc_sony-ct3/output/normal/CVS/Root
bench/sim_mc_sony-ct3/output/downsample/README
bench/sim_mc_sony-ct3/output/downsample/CVS/Entries
bench/sim_mc_sony-ct3/output/downsample/CVS/Repository
bench/sim_mc_sony-ct3/output/downsample/CVS/Root
bench/sim_mc_sony-ct3/output/CVS/Entries
bench/sim_mc_sony-ct3/output/CVS/Repository
bench/sim_mc_sony-ct3/output/CVS/Root
bench/sim_mc_sony-ct3/debug_utils/diffall
bench/sim_mc_sony-ct3/debug_utils/generate_ppm
bench/sim_mc_sony-ct3/debug_utils/showRam.awk
bench/sim_mc_sony-ct3/debug_utils/sony-ct3_disp.stat
bench/sim_mc_sony-ct3/debug_utils/CVS/Entries
bench/sim_mc_sony-ct3/debug_utils/CVS/Repository
bench/sim_mc_sony-ct3/debug_utils/CVS/Root
bench/sim_mc_sony-ct3/CVS/Entries
bench/sim_mc_sony-ct3/CVS/Repository
bench/sim_mc_sony-ct3/CVS/Root
bench/sim_mc_numbers/run
bench/sim_mc_numbers/sim.v
bench/sim_mc_numbers/output/pack/README
bench/sim_mc_numbers/output/pack/CVS/Entries
bench/sim_mc_numbers/output/pack/CVS/Repository
bench/sim_mc_numbers/output/pack/CVS/Root
bench/sim_mc_numbers/output/normal/README
bench/sim_mc_numbers/output/normal/CVS/Entries
bench/sim_mc_numbers/output/normal/CVS/Repository
bench/sim_mc_numbers/output/normal/CVS/Root
bench/sim_mc_numbers/output/downsample/README
bench/sim_mc_numbers/output/downsample/CVS/Entries
bench/sim_mc_numbers/output/downsample/CVS/Repository
bench/sim_mc_numbers/output/downsample/CVS/Root
bench/sim_mc_numbers/output/CVS/Entries
bench/sim_mc_numbers/output/CVS/Repository
bench/sim_mc_numbers/output/CVS/Root
bench/sim_mc_numbers/debug_utils/diffall
bench/sim_mc_numbers/debug_utils/generate_ppm
bench/sim_mc_numbers/debug_utils/numbers_disp.stat
bench/sim_mc_numbers/debug_utils/showRam.awk
bench/sim_mc_numbers/debug_utils/CVS/Entries
bench/sim_mc_numbers/debug_utils/CVS/Repository
bench/sim_mc_numbers/debug_utils/CVS/Root
bench/sim_mc_numbers/CVS/Entries
bench/sim_mc_numbers/CVS/Repository
bench/sim_mc_numbers/CVS/Root
bench/sim_mc_nokia6/run
bench/sim_mc_nokia6/sim.v
bench/sim_mc_nokia6/output/pack/README
bench/sim_mc_nokia6/output/pack/CVS/Entries
bench/sim_mc_nokia6/output/pack/CVS/Repository
bench/sim_mc_nokia6/output/pack/CVS/Root
bench/sim_mc_nokia6/output/normal/README
bench/sim_mc_nokia6/output/normal/CVS/Entries
bench/sim_mc_nokia6/

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 搜珍网是交换下载平台，只提供交流渠道，下载内容来自于网络，除下载问题外，其它问题请自行百度。更多...
  • 本站已设置防盗链，请勿用迅雷、QQ旋风等下载软件下载资源，下载后用WinRAR最新版进行解压.
  • 如果您发现内容无法下载，请稍后再次尝试；或换浏览器；或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎，请到消费记录里找到下载记录反馈给我们，经确认后退回积分.
  • 如下载前有疑问，可以通过点击"提供者"的名字，查看对方的联系方式，联系对方咨询.
查看所有评论

相关评论

暂无评论内容．

发表评论

*快速评论： 推荐 一般 有密码 和说明不符 不是源码或资料 文件不全 不能解压 纯粹是垃圾
*内　　容：
*验 证 码：
搜珍网 www.dssz.com

浏览历史记录

关闭