文件名称:float01092
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- 上传时间:2012-11-16
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文件大小:921.51kb
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xilinx FPGA中浮点乘法IP核的应用,已通过验证-xilinx FPGA multiply IP
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下载文件列表
float01092/float01092.cmd_log
float01092/float01092.ise
float01092/float01092.ise_ISE_Backup
float01092/float01092.lso
float01092/float01092.ngc
float01092/float01092.ngr
float01092/float01092.ntrc_log
float01092/float01092.prj
float01092/float01092.rar
float01092/float01092.restore
float01092/float01092.stx
float01092/float01092.syr
float01092/float01092.v
float01092/float01092.xst
float01092/float01092_summary.html
float01092/isim/unisim_ver.auxlib/hdllib.ref
float01092/isim/unisim_ver.auxlib/_f_d/mingw/_f_d.obj
float01092/isim/unisim_ver.auxlib/_f_d/_f_d.h
float01092/isim/unisim_ver.auxlib/_f_d_e/mingw/_f_d_e.obj
float01092/isim/unisim_ver.auxlib/_f_d_e/_f_d_e.h
float01092/isim/unisim_ver.auxlib/_f_d_r/mingw/_f_d_r.obj
float01092/isim/unisim_ver.auxlib/_f_d_r/_f_d_r.h
float01092/isim/unisim_ver.auxlib/_f_d_r_e/mingw/_f_d_r_e.obj
float01092/isim/unisim_ver.auxlib/_f_d_r_e/_f_d_r_e.h
float01092/isim/unisim_ver.auxlib/_f_d_r_s/mingw/_f_d_r_s.obj
float01092/isim/unisim_ver.auxlib/_f_d_r_s/_f_d_r_s.h
float01092/isim/unisim_ver.auxlib/_f_d_s/mingw/_f_d_s.obj
float01092/isim/unisim_ver.auxlib/_f_d_s/_f_d_s.h
float01092/isim/unisim_ver.auxlib/_g_n_d/mingw/_g_n_d.obj
float01092/isim/unisim_ver.auxlib/_g_n_d/_g_n_d.h
float01092/isim/unisim_ver.auxlib/_i_n_v/mingw/_i_n_v.obj
float01092/isim/unisim_ver.auxlib/_i_n_v/_i_n_v.h
float01092/isim/unisim_ver.auxlib/_l_u_t1/mingw/_l_u_t1.obj
float01092/isim/unisim_ver.auxlib/_l_u_t1/_l_u_t1.h
float01092/isim/unisim_ver.auxlib/_l_u_t2/mingw/_l_u_t2.obj
float01092/isim/unisim_ver.auxlib/_l_u_t2/_l_u_t2.h
float01092/isim/unisim_ver.auxlib/_l_u_t2___l/mingw/_l_u_t2___l.obj
float01092/isim/unisim_ver.auxlib/_l_u_t2___l/_l_u_t2___l.h
float01092/isim/unisim_ver.auxlib/_l_u_t3/mingw/_l_u_t3.obj
float01092/isim/unisim_ver.auxlib/_l_u_t3/_l_u_t3.h
float01092/isim/unisim_ver.auxlib/_l_u_t3___d/mingw/_l_u_t3___d.obj
float01092/isim/unisim_ver.auxlib/_l_u_t3___d/_l_u_t3___d.h
float01092/isim/unisim_ver.auxlib/_l_u_t3___l/mingw/_l_u_t3___l.obj
float01092/isim/unisim_ver.auxlib/_l_u_t3___l/_l_u_t3___l.h
float01092/isim/unisim_ver.auxlib/_l_u_t4/mingw/_l_u_t4.obj
float01092/isim/unisim_ver.auxlib/_l_u_t4/_l_u_t4.h
float01092/isim/unisim_ver.auxlib/_l_u_t4___d/mingw/_l_u_t4___d.obj
float01092/isim/unisim_ver.auxlib/_l_u_t4___d/_l_u_t4___d.h
float01092/isim/unisim_ver.auxlib/_l_u_t4___l/mingw/_l_u_t4___l.obj
float01092/isim/unisim_ver.auxlib/_l_u_t4___l/_l_u_t4___l.h
float01092/isim/unisim_ver.auxlib/_m_u_l_t___a_n_d/mingw/_m_u_l_t___a_n_d.obj
float01092/isim/unisim_ver.auxlib/_m_u_l_t___a_n_d/_m_u_l_t___a_n_d.h
float01092/isim/unisim_ver.auxlib/_m_u_x_c_y/mingw/_m_u_x_c_y.obj
float01092/isim/unisim_ver.auxlib/_m_u_x_c_y/_m_u_x_c_y.h
float01092/isim/unisim_ver.auxlib/_s_r_l16/mingw/_s_r_l16.obj
float01092/isim/unisim_ver.auxlib/_s_r_l16/_s_r_l16.h
float01092/isim/unisim_ver.auxlib/_s_r_l16_e/mingw/_s_r_l16_e.obj
float01092/isim/unisim_ver.auxlib/_s_r_l16_e/_s_r_l16_e.h
float01092/isim/unisim_ver.auxlib/_v_c_c/mingw/_v_c_c.obj
float01092/isim/unisim_ver.auxlib/_v_c_c/_v_c_c.h
float01092/isim/unisim_ver.auxlib/_x_o_r_c_y/mingw/_x_o_r_c_y.obj
float01092/isim/unisim_ver.auxlib/_x_o_r_c_y/_x_o_r_c_y.h
float01092/isim/work/float01092/float01092.h
float01092/isim/work/float01092/mingw/float01092.obj
float01092/isim/work/glbl/glbl.h
float01092/isim/work/glbl/mingw/glbl.obj
float01092/isim/work/hdllib.ref
float01092/isim/work/hdpdeps.ref
float01092/isim/work/mulf/mingw/mulf.obj
float01092/isim/work/mulf/mulf.h
float01092/isim/work/testa__v/mingw/testa__v.obj
float01092/isim/work/testa__v/testa__v.h
float01092/isim/work/testa__v/xsimtesta__v.cpp
float01092/isim/work/testb__v/mingw/testb__v.obj
float01092/isim/work/testb__v/testb__v.h
float01092/isim/work/testb__v/xsimtestb__v.cpp
float01092/isim/work/vlg28/mulf.bin
float01092/isim/work/vlg2D/glbl.bin
float01092/isim/work/vlg2E/testa__v.bin
float01092/isim/work/vlg36/float01092.bin
float01092/isim/work/vlg47/testb__v.bin
float01092/isim.cmd
float01092/isim.hdlsourcefiles
float01092/isim.log
float01092/isim.tmp_save/_1
float01092/isimwavedata.xwv
float01092/mulf.asy
float01092/mulf.ngc
float01092/mulf.sym
float01092/mulf.v
float01092/mulf.veo
float01092/mulf.vhd
float01092/mulf.vho
float01092/mulf.xco
float01092/mulf_flist.txt
float01092/mulf_readme.txt
float01092/mulf_xmdf.tcl
float01092/simulate_dofile.log
float01092/simulate_dofile.log_back
float01092/templates/coregen.xml
float01092/testa.v
float01092/testa_v_isim_beh.wfs
float01092/testb.v
float01092/testb_v_beh.prj
float01092/testb_v_isim_beh.exe
float01092/testb_v_isim_beh.wfs
float01092/xilinxsim.ini
float01092/xst/dump.xst/float01092.prj/ntrc.scr
float01092/xst/work/hdllib.ref
float01092/xst/work/vlg28/mulf.bin
float01092/xst/work/vlg36/float01092.bin
float01092/_xmsgs/fuse.xmsgs
float01092/_xmsgs/xst.xmsgs
float01092/__ISE_repository_float01092.ise_.lock
float01092/xst/dump.xst/float01092.prj/ngx/notopt
float01092/xst/dump.xst/float01092.prj/ngx/opt
float01092/isim/unisim_ver.auxlib/_f_d/mingw
float01092/isim/unisim_ver.auxlib/_f_d_e/mingw
float01092/isim/unisim_ver.auxlib/_f_d_r/mingw
float01092/isim/unisim_ve
float01092/float01092.ise
float01092/float01092.ise_ISE_Backup
float01092/float01092.lso
float01092/float01092.ngc
float01092/float01092.ngr
float01092/float01092.ntrc_log
float01092/float01092.prj
float01092/float01092.rar
float01092/float01092.restore
float01092/float01092.stx
float01092/float01092.syr
float01092/float01092.v
float01092/float01092.xst
float01092/float01092_summary.html
float01092/isim/unisim_ver.auxlib/hdllib.ref
float01092/isim/unisim_ver.auxlib/_f_d/mingw/_f_d.obj
float01092/isim/unisim_ver.auxlib/_f_d/_f_d.h
float01092/isim/unisim_ver.auxlib/_f_d_e/mingw/_f_d_e.obj
float01092/isim/unisim_ver.auxlib/_f_d_e/_f_d_e.h
float01092/isim/unisim_ver.auxlib/_f_d_r/mingw/_f_d_r.obj
float01092/isim/unisim_ver.auxlib/_f_d_r/_f_d_r.h
float01092/isim/unisim_ver.auxlib/_f_d_r_e/mingw/_f_d_r_e.obj
float01092/isim/unisim_ver.auxlib/_f_d_r_e/_f_d_r_e.h
float01092/isim/unisim_ver.auxlib/_f_d_r_s/mingw/_f_d_r_s.obj
float01092/isim/unisim_ver.auxlib/_f_d_r_s/_f_d_r_s.h
float01092/isim/unisim_ver.auxlib/_f_d_s/mingw/_f_d_s.obj
float01092/isim/unisim_ver.auxlib/_f_d_s/_f_d_s.h
float01092/isim/unisim_ver.auxlib/_g_n_d/mingw/_g_n_d.obj
float01092/isim/unisim_ver.auxlib/_g_n_d/_g_n_d.h
float01092/isim/unisim_ver.auxlib/_i_n_v/mingw/_i_n_v.obj
float01092/isim/unisim_ver.auxlib/_i_n_v/_i_n_v.h
float01092/isim/unisim_ver.auxlib/_l_u_t1/mingw/_l_u_t1.obj
float01092/isim/unisim_ver.auxlib/_l_u_t1/_l_u_t1.h
float01092/isim/unisim_ver.auxlib/_l_u_t2/mingw/_l_u_t2.obj
float01092/isim/unisim_ver.auxlib/_l_u_t2/_l_u_t2.h
float01092/isim/unisim_ver.auxlib/_l_u_t2___l/mingw/_l_u_t2___l.obj
float01092/isim/unisim_ver.auxlib/_l_u_t2___l/_l_u_t2___l.h
float01092/isim/unisim_ver.auxlib/_l_u_t3/mingw/_l_u_t3.obj
float01092/isim/unisim_ver.auxlib/_l_u_t3/_l_u_t3.h
float01092/isim/unisim_ver.auxlib/_l_u_t3___d/mingw/_l_u_t3___d.obj
float01092/isim/unisim_ver.auxlib/_l_u_t3___d/_l_u_t3___d.h
float01092/isim/unisim_ver.auxlib/_l_u_t3___l/mingw/_l_u_t3___l.obj
float01092/isim/unisim_ver.auxlib/_l_u_t3___l/_l_u_t3___l.h
float01092/isim/unisim_ver.auxlib/_l_u_t4/mingw/_l_u_t4.obj
float01092/isim/unisim_ver.auxlib/_l_u_t4/_l_u_t4.h
float01092/isim/unisim_ver.auxlib/_l_u_t4___d/mingw/_l_u_t4___d.obj
float01092/isim/unisim_ver.auxlib/_l_u_t4___d/_l_u_t4___d.h
float01092/isim/unisim_ver.auxlib/_l_u_t4___l/mingw/_l_u_t4___l.obj
float01092/isim/unisim_ver.auxlib/_l_u_t4___l/_l_u_t4___l.h
float01092/isim/unisim_ver.auxlib/_m_u_l_t___a_n_d/mingw/_m_u_l_t___a_n_d.obj
float01092/isim/unisim_ver.auxlib/_m_u_l_t___a_n_d/_m_u_l_t___a_n_d.h
float01092/isim/unisim_ver.auxlib/_m_u_x_c_y/mingw/_m_u_x_c_y.obj
float01092/isim/unisim_ver.auxlib/_m_u_x_c_y/_m_u_x_c_y.h
float01092/isim/unisim_ver.auxlib/_s_r_l16/mingw/_s_r_l16.obj
float01092/isim/unisim_ver.auxlib/_s_r_l16/_s_r_l16.h
float01092/isim/unisim_ver.auxlib/_s_r_l16_e/mingw/_s_r_l16_e.obj
float01092/isim/unisim_ver.auxlib/_s_r_l16_e/_s_r_l16_e.h
float01092/isim/unisim_ver.auxlib/_v_c_c/mingw/_v_c_c.obj
float01092/isim/unisim_ver.auxlib/_v_c_c/_v_c_c.h
float01092/isim/unisim_ver.auxlib/_x_o_r_c_y/mingw/_x_o_r_c_y.obj
float01092/isim/unisim_ver.auxlib/_x_o_r_c_y/_x_o_r_c_y.h
float01092/isim/work/float01092/float01092.h
float01092/isim/work/float01092/mingw/float01092.obj
float01092/isim/work/glbl/glbl.h
float01092/isim/work/glbl/mingw/glbl.obj
float01092/isim/work/hdllib.ref
float01092/isim/work/hdpdeps.ref
float01092/isim/work/mulf/mingw/mulf.obj
float01092/isim/work/mulf/mulf.h
float01092/isim/work/testa__v/mingw/testa__v.obj
float01092/isim/work/testa__v/testa__v.h
float01092/isim/work/testa__v/xsimtesta__v.cpp
float01092/isim/work/testb__v/mingw/testb__v.obj
float01092/isim/work/testb__v/testb__v.h
float01092/isim/work/testb__v/xsimtestb__v.cpp
float01092/isim/work/vlg28/mulf.bin
float01092/isim/work/vlg2D/glbl.bin
float01092/isim/work/vlg2E/testa__v.bin
float01092/isim/work/vlg36/float01092.bin
float01092/isim/work/vlg47/testb__v.bin
float01092/isim.cmd
float01092/isim.hdlsourcefiles
float01092/isim.log
float01092/isim.tmp_save/_1
float01092/isimwavedata.xwv
float01092/mulf.asy
float01092/mulf.ngc
float01092/mulf.sym
float01092/mulf.v
float01092/mulf.veo
float01092/mulf.vhd
float01092/mulf.vho
float01092/mulf.xco
float01092/mulf_flist.txt
float01092/mulf_readme.txt
float01092/mulf_xmdf.tcl
float01092/simulate_dofile.log
float01092/simulate_dofile.log_back
float01092/templates/coregen.xml
float01092/testa.v
float01092/testa_v_isim_beh.wfs
float01092/testb.v
float01092/testb_v_beh.prj
float01092/testb_v_isim_beh.exe
float01092/testb_v_isim_beh.wfs
float01092/xilinxsim.ini
float01092/xst/dump.xst/float01092.prj/ntrc.scr
float01092/xst/work/hdllib.ref
float01092/xst/work/vlg28/mulf.bin
float01092/xst/work/vlg36/float01092.bin
float01092/_xmsgs/fuse.xmsgs
float01092/_xmsgs/xst.xmsgs
float01092/__ISE_repository_float01092.ise_.lock
float01092/xst/dump.xst/float01092.prj/ngx/notopt
float01092/xst/dump.xst/float01092.prj/ngx/opt
float01092/isim/unisim_ver.auxlib/_f_d/mingw
float01092/isim/unisim_ver.auxlib/_f_d_e/mingw
float01092/isim/unisim_ver.auxlib/_f_d_r/mingw
float01092/isim/unisim_ve
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