文件名称:Alpha
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一款Alpha指令集的超标量处理器的Verilog源码,是学习乱序处理器的难得资料。-A superscalar Alpha processor instruction set of the Verilog source code for a processor to learn valuable information out of order.
相关搜索: superscalar
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下载文件列表
Alpha/__projnav/sumrpt_tcl.rsp
Alpha/__projnav/Alpha.gfl
Alpha/__projnav
Alpha/Project.dhp
Alpha/Alpha.ise
Alpha/Alpha.dhp
Alpha/Alpha.ise_ISE_Backup
Alpha/update_ready_bits_summary.html
Alpha/data_memory_summary.html
Alpha/bundle_info.v
Alpha/parameters.v
Alpha/pipeline.v
Alpha/CMPn.v
Alpha/DEC1_3_8.v
Alpha/MUXn.v
Alpha/RAM.v
Alpha/REGn.v
Alpha/cmov_split.v
Alpha/Decode.v
Alpha/Decoder.v
Alpha/regsD0_R0.v
Alpha/AGEN.v
Alpha/branch.v
Alpha/complex_ALU.v
Alpha/conflict_buffer.v
Alpha/execute.v
Alpha/forward.v
Alpha/forward_all.v
Alpha/multiply.v
Alpha/regs_RR_EX.v
Alpha/simple_ALU.v
Alpha/align.v
Alpha/BOB.v
Alpha/BranchDecoder.v
Alpha/BranchDecoders.v
Alpha/BTB.v
Alpha/cache_bank.v
Alpha/fetch0.v
Alpha/fetch1.v
Alpha/fetch2.v
Alpha/info.v
Alpha/insn_memory.v
Alpha/itlb.v
Alpha/l1icache.v
Alpha/NextPC.v
Alpha/PCPlus.v
Alpha/RAS.v
Alpha/regsF0.v
Alpha/regsF0_F1.v
Alpha/regsF1_F2.v
Alpha/regsF2_D0.v
Alpha/stack.v
Alpha/tables.v
Alpha/tournament_predictor.v
Alpha/dispmux.v
Alpha/forward_check.v
Alpha/get_bit.v
Alpha/get_select.v
Alpha/reg_read.v
Alpha/regfile.v
Alpha/regsI_RR.v
Alpha/Scheduler.v
Alpha/scoreboard.v
Alpha/single_check.v
Alpha/update_ready_bits.v
Alpha/data_cache_bank.v
Alpha/data_memory.v
Alpha/dtlb.v
Alpha/l1dcache.v
Alpha/membuffer.v
Alpha/memoryunit.v
Alpha/missqueue.v
Alpha/Depend_check.v
Alpha/LFST.v
Alpha/LFST_override.v
Alpha/Mapping_overide.v
Alpha/regsR0_R1.v
Alpha/regsR1_I.v
Alpha/rename0.v
Alpha/rename1.v
Alpha/SpecFreeRegList.v
Alpha/SpecRATfile.v
Alpha/SSIT.v
Alpha/SSIT_depend_check.v
Alpha/ArchRATfile.v
Alpha/regs_EX_WB.v
Alpha/regs_WB_WB.v
Alpha/ROB.v
Alpha/util.def
Alpha
Alpha/__projnav/Alpha.gfl
Alpha/__projnav
Alpha/Project.dhp
Alpha/Alpha.ise
Alpha/Alpha.dhp
Alpha/Alpha.ise_ISE_Backup
Alpha/update_ready_bits_summary.html
Alpha/data_memory_summary.html
Alpha/bundle_info.v
Alpha/parameters.v
Alpha/pipeline.v
Alpha/CMPn.v
Alpha/DEC1_3_8.v
Alpha/MUXn.v
Alpha/RAM.v
Alpha/REGn.v
Alpha/cmov_split.v
Alpha/Decode.v
Alpha/Decoder.v
Alpha/regsD0_R0.v
Alpha/AGEN.v
Alpha/branch.v
Alpha/complex_ALU.v
Alpha/conflict_buffer.v
Alpha/execute.v
Alpha/forward.v
Alpha/forward_all.v
Alpha/multiply.v
Alpha/regs_RR_EX.v
Alpha/simple_ALU.v
Alpha/align.v
Alpha/BOB.v
Alpha/BranchDecoder.v
Alpha/BranchDecoders.v
Alpha/BTB.v
Alpha/cache_bank.v
Alpha/fetch0.v
Alpha/fetch1.v
Alpha/fetch2.v
Alpha/info.v
Alpha/insn_memory.v
Alpha/itlb.v
Alpha/l1icache.v
Alpha/NextPC.v
Alpha/PCPlus.v
Alpha/RAS.v
Alpha/regsF0.v
Alpha/regsF0_F1.v
Alpha/regsF1_F2.v
Alpha/regsF2_D0.v
Alpha/stack.v
Alpha/tables.v
Alpha/tournament_predictor.v
Alpha/dispmux.v
Alpha/forward_check.v
Alpha/get_bit.v
Alpha/get_select.v
Alpha/reg_read.v
Alpha/regfile.v
Alpha/regsI_RR.v
Alpha/Scheduler.v
Alpha/scoreboard.v
Alpha/single_check.v
Alpha/update_ready_bits.v
Alpha/data_cache_bank.v
Alpha/data_memory.v
Alpha/dtlb.v
Alpha/l1dcache.v
Alpha/membuffer.v
Alpha/memoryunit.v
Alpha/missqueue.v
Alpha/Depend_check.v
Alpha/LFST.v
Alpha/LFST_override.v
Alpha/Mapping_overide.v
Alpha/regsR0_R1.v
Alpha/regsR1_I.v
Alpha/rename0.v
Alpha/rename1.v
Alpha/SpecFreeRegList.v
Alpha/SpecRATfile.v
Alpha/SSIT.v
Alpha/SSIT_depend_check.v
Alpha/ArchRATfile.v
Alpha/regs_EX_WB.v
Alpha/regs_WB_WB.v
Alpha/ROB.v
Alpha/util.def
Alpha
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