利用 FPGA 实现大型设计时，可能需要FPGA 具有以多个时钟运行的多重数据通路，这种

多时钟FPGA 设计必须特别小心，需要注意最大时钟速率、抖动、最大时钟数、异步时钟

设计和时钟/数据关系。设计过程中最重要的一步是确定要用多少个不同的时钟，以及如何

进行布线，本文将对这些设计策略深入阐述。-Using FPGA to achieve large-scale design, may need to run the FPGA with multiple clocks to multiple data paths, multiple clock FPGA design that must be especially careful to note the maximum clock rate, jitter, maximum number of clocks, asynchronous clock design and clock/data relationship. The design of the most important step is to determine how many different clocks to use, and how to layout, this paper will further elaborate the design strategy.