文件名称:I2C_Verilog_Model
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- 上传时间:2012-11-16
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文件大小:356.18kb
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该源程序包是I2C的Verilog语言模型,包括以下4个部分:RTL源代码,测试平台,软件仿真代码,说明文件。-This source package is I2C bus model based on Verilog language. It has the following 4 parts: RTL code, testbench, sofeware simulating code, help document.
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下载文件列表
I2C_Verilog_Model/bench/verilog/i2c_slave_model.v
I2C_Verilog_Model/bench/verilog/spi_slave_model.v
I2C_Verilog_Model/bench/verilog/tst_bench_top.v
I2C_Verilog_Model/bench/verilog/wb_master_model.v
I2C_Verilog_Model/doc/i2c_specs.pdf
I2C_Verilog_Model/rtl/verilog/i2c_master_bit_ctrl.v
I2C_Verilog_Model/rtl/verilog/i2c_master_byte_ctrl.v
I2C_Verilog_Model/rtl/verilog/i2c_master_defines.v
I2C_Verilog_Model/rtl/verilog/i2c_master_top.v
I2C_Verilog_Model/rtl/verilog/timescale.v
I2C_Verilog_Model/sim/i2c_verilog/run/bench.vcd
I2C_Verilog_Model/sim/i2c_verilog/run/ncverilog.key
I2C_Verilog_Model/sim/i2c_verilog/run/ncverilog.log
I2C_Verilog_Model/sim/i2c_verilog/run/run
I2C_Verilog_Model/sim/i2c_verilog/run/INCA_libs
I2C_Verilog_Model/sim/i2c_verilog/run/waves
I2C_Verilog_Model/sim/i2c_verilog/run
I2C_Verilog_Model/bench/verilog
I2C_Verilog_Model/rtl/verilog
I2C_Verilog_Model/sim/i2c_verilog
I2C_Verilog_Model/bench
I2C_Verilog_Model/doc
I2C_Verilog_Model/rtl
I2C_Verilog_Model/sim
I2C_Verilog_Model
I2C_Verilog_Model/bench/verilog/spi_slave_model.v
I2C_Verilog_Model/bench/verilog/tst_bench_top.v
I2C_Verilog_Model/bench/verilog/wb_master_model.v
I2C_Verilog_Model/doc/i2c_specs.pdf
I2C_Verilog_Model/rtl/verilog/i2c_master_bit_ctrl.v
I2C_Verilog_Model/rtl/verilog/i2c_master_byte_ctrl.v
I2C_Verilog_Model/rtl/verilog/i2c_master_defines.v
I2C_Verilog_Model/rtl/verilog/i2c_master_top.v
I2C_Verilog_Model/rtl/verilog/timescale.v
I2C_Verilog_Model/sim/i2c_verilog/run/bench.vcd
I2C_Verilog_Model/sim/i2c_verilog/run/ncverilog.key
I2C_Verilog_Model/sim/i2c_verilog/run/ncverilog.log
I2C_Verilog_Model/sim/i2c_verilog/run/run
I2C_Verilog_Model/sim/i2c_verilog/run/INCA_libs
I2C_Verilog_Model/sim/i2c_verilog/run/waves
I2C_Verilog_Model/sim/i2c_verilog/run
I2C_Verilog_Model/bench/verilog
I2C_Verilog_Model/rtl/verilog
I2C_Verilog_Model/sim/i2c_verilog
I2C_Verilog_Model/bench
I2C_Verilog_Model/doc
I2C_Verilog_Model/rtl
I2C_Verilog_Model/sim
I2C_Verilog_Model
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