文件名称:Chapter4-Sample
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I2C总线和RS- 232串行端口已成为嵌入式系统主要的数据交换接口,可以实现嵌入式系统与外围设备之间的数据传输[2]。但是,在E2PRO里面需要一些I2C总线来写入数据,因为数据技术上的原因,如果没有其他办法,将无法达到所要求的传输速率;同样,对于RS -232串行端口,如果收发程序时处理不当,-I2C-bus and RS-232 serial port has become a major embedded systems for data exchange interfaces, embedded systems and can achieve data transfer between peripheral devices [2]. However, there need some I2C bus E2PRO to write data because the data for technical reasons, if no other way, it will not achieve the required transmission rate Similarly, for the RS-232 serial port, if the sending and receiving treatment program improper
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下载文件列表
Chapter4 Sample/使用说明.txt
Chapter4 Sample/I2C/I2C.dhp
Chapter4 Sample/I2C/I2C.npl
Chapter4 Sample/I2C/__projnav.log
Chapter4 Sample/I2C/automake.log
Chapter4 Sample/I2C/coregen.log
Chapter4 Sample/I2C/coregen.prj
Chapter4 Sample/I2C/i2c_master_bit_ctrl.cmd_log
Chapter4 Sample/I2C/i2c_master_bit_ctrl.lso
Chapter4 Sample/I2C/i2c_master_bit_ctrl.ngc
Chapter4 Sample/I2C/i2c_master_bit_ctrl.ngr
Chapter4 Sample/I2C/i2c_master_bit_ctrl.prj
Chapter4 Sample/I2C/i2c_master_bit_ctrl.stx
Chapter4 Sample/I2C/i2c_master_bit_ctrl.syr
Chapter4 Sample/I2C/i2c_master_bit_ctrl.v
Chapter4 Sample/I2C/i2c_master_bit_ctrl.v.bak
Chapter4 Sample/I2C/i2c_master_bit_ctrl_vhdl.prj
Chapter4 Sample/I2C/i2c_master_byte_ctrl.cmd_log
Chapter4 Sample/I2C/i2c_master_byte_ctrl.lso
Chapter4 Sample/I2C/i2c_master_byte_ctrl.ngc
Chapter4 Sample/I2C/i2c_master_byte_ctrl.ngr
Chapter4 Sample/I2C/i2c_master_byte_ctrl.prj
Chapter4 Sample/I2C/i2c_master_byte_ctrl.stx
Chapter4 Sample/I2C/i2c_master_byte_ctrl.syr
Chapter4 Sample/I2C/i2c_master_byte_ctrl.v
Chapter4 Sample/I2C/i2c_master_byte_ctrl.v.bak
Chapter4 Sample/I2C/i2c_master_byte_ctrl_vhdl.prj
Chapter4 Sample/I2C/i2c_master_defines.v
Chapter4 Sample/I2C/i2c_master_defines.v.bak
Chapter4 Sample/I2C/i2c_master_top.cmd_log
Chapter4 Sample/I2C/i2c_master_top.lso
Chapter4 Sample/I2C/i2c_master_top.ngc
Chapter4 Sample/I2C/i2c_master_top.ngr
Chapter4 Sample/I2C/i2c_master_top.prj
Chapter4 Sample/I2C/i2c_master_top.stx
Chapter4 Sample/I2C/i2c_master_top.syr
Chapter4 Sample/I2C/i2c_master_top.v
Chapter4 Sample/I2C/i2c_master_top.v.bak
Chapter4 Sample/I2C/i2c_master_top_vhdl.prj
Chapter4 Sample/I2C/i2c_slave_model.fdo
Chapter4 Sample/I2C/i2c_slave_model.ndo
Chapter4 Sample/I2C/i2c_slave_model.udo
Chapter4 Sample/I2C/i2c_slave_model.v
Chapter4 Sample/I2C/i2c_slave_model.v.bak
Chapter4 Sample/I2C/prjname.lso
Chapter4 Sample/I2C/timescale.v
Chapter4 Sample/I2C/transcript
Chapter4 Sample/I2C/tst_bench_top.v
Chapter4 Sample/I2C/wb_master_model.v
Chapter4 Sample/I2C/wb_master_model.v.bak
Chapter4 Sample/I2C/xst/work/hdllib.ref
Chapter4 Sample/I2C/xst/work/vlg67/i2c_master_top.bin
Chapter4 Sample/I2C/xst/work/vlg5C/i2c_master_byte_ctrl.bin
Chapter4 Sample/I2C/xst/work/vlg07/i2c_master_bit_ctrl.bin
Chapter4 Sample/I2C/work/_info
Chapter4 Sample/I2C/work/i2c_slave_model/_primary.dat
Chapter4 Sample/I2C/work/i2c_slave_model/_primary.vhd
Chapter4 Sample/I2C/work/i2c_slave_model/verilog.asm
Chapter4 Sample/I2C/work/glbl/_primary.dat
Chapter4 Sample/I2C/work/glbl/_primary.vhd
Chapter4 Sample/I2C/work/glbl/verilog.asm
Chapter4 Sample/I2C/__projnav/I2C.gfl
Chapter4 Sample/I2C/__projnav/I2C_flowplus.gfl
Chapter4 Sample/I2C/__projnav/coregen.rsp
Chapter4 Sample/I2C/__projnav/i2c_master_bit_ctrl.xst
Chapter4 Sample/I2C/__projnav/i2c_master_byte_ctrl.xst
Chapter4 Sample/I2C/__projnav/i2c_master_top.xst
Chapter4 Sample/I2C/__projnav/runXst_tcl.rsp
Chapter4 Sample/I2C/__projnav/xst_sprjTOstx_tcl.rsp
Chapter4 Sample/I2C/xst/work/vlg67
Chapter4 Sample/I2C/xst/work/vlg5C
Chapter4 Sample/I2C/xst/work/vlg07
Chapter4 Sample/I2C/xst/work
Chapter4 Sample/I2C/work/i2c_slave_model
Chapter4 Sample/I2C/work/glbl
Chapter4 Sample/I2C/xst
Chapter4 Sample/I2C/work
Chapter4 Sample/I2C/__projnav
Chapter4 Sample/I2C
Chapter4 Sample
Chapter4 Sample/I2C/I2C.dhp
Chapter4 Sample/I2C/I2C.npl
Chapter4 Sample/I2C/__projnav.log
Chapter4 Sample/I2C/automake.log
Chapter4 Sample/I2C/coregen.log
Chapter4 Sample/I2C/coregen.prj
Chapter4 Sample/I2C/i2c_master_bit_ctrl.cmd_log
Chapter4 Sample/I2C/i2c_master_bit_ctrl.lso
Chapter4 Sample/I2C/i2c_master_bit_ctrl.ngc
Chapter4 Sample/I2C/i2c_master_bit_ctrl.ngr
Chapter4 Sample/I2C/i2c_master_bit_ctrl.prj
Chapter4 Sample/I2C/i2c_master_bit_ctrl.stx
Chapter4 Sample/I2C/i2c_master_bit_ctrl.syr
Chapter4 Sample/I2C/i2c_master_bit_ctrl.v
Chapter4 Sample/I2C/i2c_master_bit_ctrl.v.bak
Chapter4 Sample/I2C/i2c_master_bit_ctrl_vhdl.prj
Chapter4 Sample/I2C/i2c_master_byte_ctrl.cmd_log
Chapter4 Sample/I2C/i2c_master_byte_ctrl.lso
Chapter4 Sample/I2C/i2c_master_byte_ctrl.ngc
Chapter4 Sample/I2C/i2c_master_byte_ctrl.ngr
Chapter4 Sample/I2C/i2c_master_byte_ctrl.prj
Chapter4 Sample/I2C/i2c_master_byte_ctrl.stx
Chapter4 Sample/I2C/i2c_master_byte_ctrl.syr
Chapter4 Sample/I2C/i2c_master_byte_ctrl.v
Chapter4 Sample/I2C/i2c_master_byte_ctrl.v.bak
Chapter4 Sample/I2C/i2c_master_byte_ctrl_vhdl.prj
Chapter4 Sample/I2C/i2c_master_defines.v
Chapter4 Sample/I2C/i2c_master_defines.v.bak
Chapter4 Sample/I2C/i2c_master_top.cmd_log
Chapter4 Sample/I2C/i2c_master_top.lso
Chapter4 Sample/I2C/i2c_master_top.ngc
Chapter4 Sample/I2C/i2c_master_top.ngr
Chapter4 Sample/I2C/i2c_master_top.prj
Chapter4 Sample/I2C/i2c_master_top.stx
Chapter4 Sample/I2C/i2c_master_top.syr
Chapter4 Sample/I2C/i2c_master_top.v
Chapter4 Sample/I2C/i2c_master_top.v.bak
Chapter4 Sample/I2C/i2c_master_top_vhdl.prj
Chapter4 Sample/I2C/i2c_slave_model.fdo
Chapter4 Sample/I2C/i2c_slave_model.ndo
Chapter4 Sample/I2C/i2c_slave_model.udo
Chapter4 Sample/I2C/i2c_slave_model.v
Chapter4 Sample/I2C/i2c_slave_model.v.bak
Chapter4 Sample/I2C/prjname.lso
Chapter4 Sample/I2C/timescale.v
Chapter4 Sample/I2C/transcript
Chapter4 Sample/I2C/tst_bench_top.v
Chapter4 Sample/I2C/wb_master_model.v
Chapter4 Sample/I2C/wb_master_model.v.bak
Chapter4 Sample/I2C/xst/work/hdllib.ref
Chapter4 Sample/I2C/xst/work/vlg67/i2c_master_top.bin
Chapter4 Sample/I2C/xst/work/vlg5C/i2c_master_byte_ctrl.bin
Chapter4 Sample/I2C/xst/work/vlg07/i2c_master_bit_ctrl.bin
Chapter4 Sample/I2C/work/_info
Chapter4 Sample/I2C/work/i2c_slave_model/_primary.dat
Chapter4 Sample/I2C/work/i2c_slave_model/_primary.vhd
Chapter4 Sample/I2C/work/i2c_slave_model/verilog.asm
Chapter4 Sample/I2C/work/glbl/_primary.dat
Chapter4 Sample/I2C/work/glbl/_primary.vhd
Chapter4 Sample/I2C/work/glbl/verilog.asm
Chapter4 Sample/I2C/__projnav/I2C.gfl
Chapter4 Sample/I2C/__projnav/I2C_flowplus.gfl
Chapter4 Sample/I2C/__projnav/coregen.rsp
Chapter4 Sample/I2C/__projnav/i2c_master_bit_ctrl.xst
Chapter4 Sample/I2C/__projnav/i2c_master_byte_ctrl.xst
Chapter4 Sample/I2C/__projnav/i2c_master_top.xst
Chapter4 Sample/I2C/__projnav/runXst_tcl.rsp
Chapter4 Sample/I2C/__projnav/xst_sprjTOstx_tcl.rsp
Chapter4 Sample/I2C/xst/work/vlg67
Chapter4 Sample/I2C/xst/work/vlg5C
Chapter4 Sample/I2C/xst/work/vlg07
Chapter4 Sample/I2C/xst/work
Chapter4 Sample/I2C/work/i2c_slave_model
Chapter4 Sample/I2C/work/glbl
Chapter4 Sample/I2C/xst
Chapter4 Sample/I2C/work
Chapter4 Sample/I2C/__projnav
Chapter4 Sample/I2C
Chapter4 Sample
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