test1/alu.v
test1/encode.v
test1/w.v
test1/test1.cr.mti
test1/ram_sel_wdrd.v
test1/sel_tmp2.v
test1/clock.v
test1/pc.v
test1/stack.v
test1/ir.v
test1/work/_info
test1/work/alu/_primary.vhd
test1/work/alu/verilog.asm
test1/work/alu/_primary.dat
test1/work/alu
test1/work/clock/_primary.vhd
test1/work/clock/verilog.asm
test1/work/clock/_primary.dat
test1/work/clock
test1/work/encode/_primary.vhd
test1/work/encode/verilog.asm
test1/work/encode/_primary.dat
test1/work/encode
test1/work/ir/_primary.vhd
test1/work/ir/verilog.asm
test1/work/ir/_primary.dat
test1/work/ir
test1/work/pc/_primary.vhd
test1/work/pc/verilog.asm
test1/work/pc/_primary.dat
test1/work/pc
test1/work/ram_sel_wdrd/_primary.vhd
test1/work/ram_sel_wdrd/verilog.asm
test1/work/ram_sel_wdrd/_primary.dat
test1/work/ram_sel_wdrd
test1/work/sel_tmp2/_primary.vhd
test1/work/sel_tmp2/verilog.asm
test1/work/sel_tmp2/_primary.dat
test1/work/sel_tmp2
test1/work/stack/_primary.vhd
test1/work/stack/verilog.asm
test1/work/stack/_primary.dat
test1/work/stack
test1/work/w/_primary.vhd
test1/work/w/verilog.asm
test1/work/w/_primary.dat
test1/work/w
test1/work/risc_mcu/_primary.vhd
test1/work/risc_mcu/verilog.asm
test1/work/risc_mcu/_primary.dat
test1/work/risc_mcu
test1/work/test1_cpu/_primary.vhd
test1/work/test1_cpu/verilog.asm
test1/work/test1_cpu/_primary.dat
test1/work/test1_cpu
test1/work
test1/alu.v.bak
test1/vish_stacktrace.vstf
test1/pc.v.bak
test1/stack.v.bak
test1/test1.mpf
test1/test1_cpu.v
test1/test1_cpu.v.bak
test1/transcript
test1/vsim.wlf
test1/encode.v.bak
test1/w.v.bak
test1/ir.v.bak
test1
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