文件名称:LED_7seg
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- 上传时间:2012-11-16
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文件大小:214.8kb
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FPGA的7段数码管程序,用verilog编写,很好的程序,不要错过啊-The 7-segment FPGA program written with verilog, very good program, do not miss ah
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下载文件列表
LED_7seg/
LED_7seg/component/
LED_7seg/constraint/
LED_7seg/coreconsole/
LED_7seg/designer/
LED_7seg/designer/impl1/
LED_7seg/designer/impl1/designer.log
LED_7seg/designer/impl1/designer_genhdl.log
LED_7seg/designer/impl1/Display_7seg.adb
LED_7seg/designer/impl1/Display_7seg.dtf/
LED_7seg/designer/impl1/Display_7seg.dtf/verify.log
LED_7seg/designer/impl1/Display_7seg.ide_des
LED_7seg/designer/impl1/Display_7seg.stp
LED_7seg/designer/impl1/Display_7seg.tcl
LED_7seg/designer/impl1/Display_7seg_fp/
LED_7seg/designer/impl1/Display_7seg_fp/Display_7seg.log
LED_7seg/designer/impl1/Display_7seg_fp/Display_7seg.pro
LED_7seg/designer/impl1/Display_7seg_fp/projectData/
LED_7seg/designer/impl1/Display_7seg_fp/projectData/Display_7seg.stp
LED_7seg/designer/impl1/simulation/
LED_7seg/hdl/
LED_7seg/hdl/Display_7seg.v
LED_7seg/LED_7seg.prj
LED_7seg/LED_7seg.prj.convert.7.3.bak
LED_7seg/phy_synthesis/
LED_7seg/simulation/
LED_7seg/simulation/meminit.dat
LED_7seg/simulation/modelsim.ini
LED_7seg/simulation/modelsim.ini.sav
LED_7seg/smartgen/
LED_7seg/smartgen/smartgen.aws
LED_7seg/stimulus/
LED_7seg/synthesis/
LED_7seg/synthesis/Display_7seg.areasrr
LED_7seg/synthesis/Display_7seg.edn
LED_7seg/synthesis/Display_7seg.fse
LED_7seg/synthesis/Display_7seg.map
LED_7seg/synthesis/Display_7seg.sap
LED_7seg/synthesis/Display_7seg.sdf
LED_7seg/synthesis/Display_7seg.srd
LED_7seg/synthesis/Display_7seg.srm
LED_7seg/synthesis/Display_7seg.srr
LED_7seg/synthesis/Display_7seg.srs
LED_7seg/synthesis/Display_7seg.tap
LED_7seg/synthesis/Display_7seg.tlg
LED_7seg/synthesis/Display_7seg.v
LED_7seg/synthesis/Display_7seg_sdc.sdc
LED_7seg/synthesis/Display_7seg_syn.prj
LED_7seg/synthesis/stdout.log
LED_7seg/synthesis/syntmp/
LED_7seg/synthesis/syntmp/Display_7seg.msg
LED_7seg/synthesis/syntmp/Display_7seg.plg
LED_7seg/synthesis/syntmp/latuch.msg
LED_7seg/synthesis/syntmp/latuch.plg
LED_7seg/synthesis/syntmp/sap.log
LED_7seg/synthesis/traplog.tlg
LED_7seg/viewdraw/
LED_7seg/viewdraw/sch/
LED_7seg/viewdraw/sym/
LED_7seg/viewdraw/vf/
LED_7seg/viewdraw/vf/project.lst
LED_7seg/viewdraw/viewdraw.ini
LED_7seg/viewdraw/wir/
LED_7seg/component/
LED_7seg/constraint/
LED_7seg/coreconsole/
LED_7seg/designer/
LED_7seg/designer/impl1/
LED_7seg/designer/impl1/designer.log
LED_7seg/designer/impl1/designer_genhdl.log
LED_7seg/designer/impl1/Display_7seg.adb
LED_7seg/designer/impl1/Display_7seg.dtf/
LED_7seg/designer/impl1/Display_7seg.dtf/verify.log
LED_7seg/designer/impl1/Display_7seg.ide_des
LED_7seg/designer/impl1/Display_7seg.stp
LED_7seg/designer/impl1/Display_7seg.tcl
LED_7seg/designer/impl1/Display_7seg_fp/
LED_7seg/designer/impl1/Display_7seg_fp/Display_7seg.log
LED_7seg/designer/impl1/Display_7seg_fp/Display_7seg.pro
LED_7seg/designer/impl1/Display_7seg_fp/projectData/
LED_7seg/designer/impl1/Display_7seg_fp/projectData/Display_7seg.stp
LED_7seg/designer/impl1/simulation/
LED_7seg/hdl/
LED_7seg/hdl/Display_7seg.v
LED_7seg/LED_7seg.prj
LED_7seg/LED_7seg.prj.convert.7.3.bak
LED_7seg/phy_synthesis/
LED_7seg/simulation/
LED_7seg/simulation/meminit.dat
LED_7seg/simulation/modelsim.ini
LED_7seg/simulation/modelsim.ini.sav
LED_7seg/smartgen/
LED_7seg/smartgen/smartgen.aws
LED_7seg/stimulus/
LED_7seg/synthesis/
LED_7seg/synthesis/Display_7seg.areasrr
LED_7seg/synthesis/Display_7seg.edn
LED_7seg/synthesis/Display_7seg.fse
LED_7seg/synthesis/Display_7seg.map
LED_7seg/synthesis/Display_7seg.sap
LED_7seg/synthesis/Display_7seg.sdf
LED_7seg/synthesis/Display_7seg.srd
LED_7seg/synthesis/Display_7seg.srm
LED_7seg/synthesis/Display_7seg.srr
LED_7seg/synthesis/Display_7seg.srs
LED_7seg/synthesis/Display_7seg.tap
LED_7seg/synthesis/Display_7seg.tlg
LED_7seg/synthesis/Display_7seg.v
LED_7seg/synthesis/Display_7seg_sdc.sdc
LED_7seg/synthesis/Display_7seg_syn.prj
LED_7seg/synthesis/stdout.log
LED_7seg/synthesis/syntmp/
LED_7seg/synthesis/syntmp/Display_7seg.msg
LED_7seg/synthesis/syntmp/Display_7seg.plg
LED_7seg/synthesis/syntmp/latuch.msg
LED_7seg/synthesis/syntmp/latuch.plg
LED_7seg/synthesis/syntmp/sap.log
LED_7seg/synthesis/traplog.tlg
LED_7seg/viewdraw/
LED_7seg/viewdraw/sch/
LED_7seg/viewdraw/sym/
LED_7seg/viewdraw/vf/
LED_7seg/viewdraw/vf/project.lst
LED_7seg/viewdraw/viewdraw.ini
LED_7seg/viewdraw/wir/
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