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文件名称:Example-6-1

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [WORD]
  • 上传时间：
    2012-11-16
  • 文件大小：
    82kb
  • 已下载：
    0次
  • 提 供 者：
    h*****
  • 相关连接：
    无
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修正介绍说明

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1.　　Example-6-1\FSM\state1目录下为一段式FSM描述方法源码

2.　　Example-6-1\FSM\state2目录下为两段式FSM描述方法源码

3.　　Example-6-1\FSM\state3目录下为三段式FSM描述方法源码

4.　　Example-6-1\FSM\ state_default目录下为添加了default默认状态的源码

-1. Example-6-1 \ FSM \ state1 directory FSM descr iption method for the source code for some type 2. Example-6-1 \ FSM \ state2 directory FSM descr iption method for the two-stage source 3. Example-6-1 \ FSM \ state3 directory FSM descr iption method for the three-stage source 4. Example-6-1 \ FSM \ state_default added a default directory for the default state of the source
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Example-6-1/
Example-6-1/FSM/
Example-6-1/FSM/state1/
Example-6-1/FSM/state1/rev_1/
Example-6-1/FSM/state1/rev_1/AutoConstraint_state1.sdc
Example-6-1/FSM/state1/rev_1/fsmviewer.fsm
Example-6-1/FSM/state1/rev_1/generic.fse
Example-6-1/FSM/state1/rev_1/generic.srd
Example-6-1/FSM/state1/rev_1/NS.txt
Example-6-1/FSM/state1/rev_1/state1.edn
Example-6-1/FSM/state1/rev_1/state1.prf
Example-6-1/FSM/state1/rev_1/state1.srm
Example-6-1/FSM/state1/rev_1/state1.srr
Example-6-1/FSM/state1/rev_1/state1.srs
Example-6-1/FSM/state1/rev_1/state1.tlg
Example-6-1/FSM/state1/rev_1/state1.vqm
Example-6-1/FSM/state1/rev_1/syntmp/
Example-6-1/FSM/state1/rev_1/syntmp/state1.msg
Example-6-1/FSM/state1/rev_1/syntmp/state1.plg
Example-6-1/FSM/state1/rev_1/verif/
Example-6-1/FSM/state1/rev_1/verif/state1.vif
Example-6-1/FSM/state1/state1.prd
Example-6-1/FSM/state1/state1.prj
Example-6-1/FSM/state1/state1.v
Example-6-1/FSM/state2/
Example-6-1/FSM/state2/rev_1/
Example-6-1/FSM/state2/rev_1/AutoConstraint_state2.sdc
Example-6-1/FSM/state2/rev_1/CS.txt
Example-6-1/FSM/state2/rev_1/fsmviewer.fsm
Example-6-1/FSM/state2/rev_1/generic.fse
Example-6-1/FSM/state2/rev_1/generic.srd
Example-6-1/FSM/state2/rev_1/rpt_state2.areasrr
Example-6-1/FSM/state2/rev_1/rpt_state2_areasrr.htm
Example-6-1/FSM/state2/rev_1/state2.edn
Example-6-1/FSM/state2/rev_1/state2.fse
Example-6-1/FSM/state2/rev_1/state2.prf
Example-6-1/FSM/state2/rev_1/state2.srd
Example-6-1/FSM/state2/rev_1/state2.srm
Example-6-1/FSM/state2/rev_1/state2.srr
Example-6-1/FSM/state2/rev_1/state2.srs
Example-6-1/FSM/state2/rev_1/state2.sxr
Example-6-1/FSM/state2/rev_1/state2.tcl
Example-6-1/FSM/state2/rev_1/state2.tlg
Example-6-1/FSM/state2/rev_1/state2.vqm
Example-6-1/FSM/state2/rev_1/state2.xrf
Example-6-1/FSM/state2/rev_1/state2_cons.tcl
Example-6-1/FSM/state2/rev_1/state2_fsm.sdc
Example-6-1/FSM/state2/rev_1/state2_rm.tcl
Example-6-1/FSM/state2/rev_1/syntmp/
Example-6-1/FSM/state2/rev_1/syntmp/fsm_tmp_cons_ui.tcl
Example-6-1/FSM/state2/rev_1/syntmp/state2.msg
Example-6-1/FSM/state2/rev_1/syntmp/state2.plg
Example-6-1/FSM/state2/rev_1/syntmp/state2_cons_ui.tcl
Example-6-1/FSM/state2/rev_1/verif/
Example-6-1/FSM/state2/rev_1/verif/state2.vif
Example-6-1/FSM/state2/state2.prd
Example-6-1/FSM/state2/state2.prj
Example-6-1/FSM/state2/state2.v
Example-6-1/FSM/state3/
Example-6-1/FSM/state3/rev_2/
Example-6-1/FSM/state3/rev_2/AutoConstraint_state2.sdc
Example-6-1/FSM/state3/rev_2/CS.txt
Example-6-1/FSM/state3/rev_2/fsmviewer.fsm
Example-6-1/FSM/state3/rev_2/generic.fse
Example-6-1/FSM/state3/rev_2/generic.srd
Example-6-1/FSM/state3/rev_2/state3.edn
Example-6-1/FSM/state3/rev_2/state3.prf
Example-6-1/FSM/state3/rev_2/state3.srm
Example-6-1/FSM/state3/rev_2/state3.srr
Example-6-1/FSM/state3/rev_2/state3.srs
Example-6-1/FSM/state3/rev_2/state3.tlg
Example-6-1/FSM/state3/rev_2/syntmp/
Example-6-1/FSM/state3/rev_2/syntmp/state3.plg
Example-6-1/FSM/state3/state3.prd
Example-6-1/FSM/state3/state3.prj
Example-6-1/FSM/state3/state3.v
Example-6-1/FSM/state_default/
Example-6-1/FSM/state_default/rev_2/
Example-6-1/FSM/state_default/rev_2/AutoConstraint_state2_default.sdc
Example-6-1/FSM/state_default/rev_2/CS.txt
Example-6-1/FSM/state_default/rev_2/fsmviewer.fsm
Example-6-1/FSM/state_default/rev_2/generic.fse
Example-6-1/FSM/state_default/rev_2/generic.srd
Example-6-1/FSM/state_default/rev_2/state2_default.edn
Example-6-1/FSM/state_default/rev_2/state2_default.prf
Example-6-1/FSM/state_default/rev_2/state2_default.srm
Example-6-1/FSM/state_default/rev_2/state2_default.srr
Example-6-1/FSM/state_default/rev_2/state2_default.srs
Example-6-1/FSM/state_default/rev_2/state2_default.tlg
Example-6-1/FSM/state_default/rev_2/syntmp/
Example-6-1/FSM/state_default/rev_2/syntmp/state2_default.plg
Example-6-1/FSM/state_default/state2_default.v
Example-6-1/FSM/state_default/state_default.prd
Example-6-1/FSM/state_default/state_default.prj
Example-6-1/示例说明.doc

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